Our second design attempt will be a Z80 running at 4 MHz, and having 64K of dynamic memory. It is essentially the same as the first example except that we replaced the nice, easy to use, DRAM devices with some older 64K by 1 parts. These devices require RAS ONLY refresh. We will use the refresh facility built into the Z80 CPU to perform this refresh for us. Since that is the only difference, we will not go through describing the other portions again. Instead we will concentrate on the differences.
On page 2 we see the heart of the design, our DRAM controller. It LOOKS just like the one in our first example, but it isn't. Examine the 74157 multiplexer inputs carefully, and compare them to the first example.
In example 1 we connected A00 through A07 to the "A" inputs of the multiplexes. In the second example we connected A00 through A07 to the "B" inputs. Why would we do that?
In the first design example we were implementing CAS before RAS refresh, so the exact ordering of the address lines was not important. In this example we are implementing RAS ONLY refresh. As stated above, we want to use the refresh facility designed into the Z80 CPU chip to do this. After all, why should we make life any harder on us than it has to be? It turns out that the devices selected in this design example, a HITACHI 4864, can be refreshed in 128 accesses. This will work with what the Z80 provides.
During a refresh cycle the Z80 outputs the refresh address on its' A00 through A06 address pins. This address needs to be allowed to flow through the multiplexers and be presented to the DRAM chips. If we examine page 2 of the schematic we will discover that the select pin of the multiplexers is high before RAS occurs. We can confirm this by examining the PAL equations for RAMSEL and RAS.
/RAMSEL = /MREQ * RFSH ; THE WHOLE 64K IS DRAM /RAS = /MREQ * STARTUP * /WR * RFSH ; ONLY DO WRITES DURING STARTUP + /MREQ * /STARTUP * RFSH ; ALL ACCESSES AFTER STARTUP + /MREQ * /RFSH ; REFRESH IS RAS ONLY
Note that RAMSEL and RAS effectively have the same equation after STARTUP goes low; whenever MREQ goes active, they do too, except for during refresh. If we examine page 2 of the schematic we find that the multiplexer control signal comes from the first tap of the delay line. It will go low one time delay AFTER RAMSEL does. Therefore, at the time RAMSEL, and RAS, goes low, the control signal will be high.
During refresh we want to have the Z80's A00 through A06 used as row addresses, and thus the refresh address. To do this then, we have to connect them to the "B" inputs of the multiplexers.
Another difference in the dynamic memory design of circuit 2 is the memory chips themselves. The parts selected for this design have separate input and output pins. You can see the memory devices on page 3 of the schematics. Since these devices have separate I/O pins I decided to implement them that way. I could have tied the two pins together, and used the same control logic I did on the last design, but I decided that I would do it differently.
When implementing the separate I/O pin design, a 74LS244 is used to connect the data out pin to the Z80's data bus when needed. The PAL on page 2 generates a signal, EN245, to do this. It is only enabled for memory reads after STARTUP goes low. For writes, EN245 remains high, and the 74LS244 is disabled.
What does this buy us? Where is the advantage in this approach? What it buys us is speed on writes. Since we don't have to do early writes, we can generate the same timing for reads and for writes. The Z80 will pulse WR* late in the bus cycle to strobe the data into the memories.
The DRAMs see this as a read-modify-write cycle. After RAS and CAS have been cycled, the memory device will access the location specified, and present that data to its' output pin. This doesn't cause any problem because the 74LS244 is disabled. Later the Z80 places data to be written on the data bus, and pulses the WR* pin. No problem. The memory device accepts the data and writes it to the same location. The output pins will continue to have the data originally stored in the specified location.
By being able to cycle RAS and CAS earlier in the memory cycle, the memory system accesses faster. This may not make much difference with a Z80 running at 4 MHZ, but it might at 10 MHZ. I once ran a Z8001 at 10 MHZ with 150 ns DRAMS using this technique, and no wait states. It ONLY works with dynamic ram devices with separate I/O pins, but it is worth remembering if you ever have the occasion to be working with these parts.
Another difference between this design example, and the first one, is visible on page 2 of the schematics. The WE* pin of the DRAMs is driven by WR* still, but WR* is buffered by two stages of a 74F04. This double inversion results in the same signal polarity as WR*, but doesn't load the WR* pin as much as it would if we didn't buffer it. The extra delay of the two inverter stages is negligible in this design.
The memory array in this design is bigger than the first example since we have eight devices instead of two. This means more capacitance. The HITACHI data book, from which these devices were selected says that the RAS, CAS, and WE pins are 10pf, while all others are 7pf. At 10pf the load on RAS, CAS, and WE is now 80pf. The load on the address lines, and data lines, is 56pf. This is not bad, but it is becoming noticeable. This is why we buffered and terminated the WE driver.
/* Also: CKT2.PDS and compiled JEDEC: CKT2.JED */
;PALASM Design Description ;---------------------------------- Declaration Segment ------------ TITLE SAMPLE Z80 DESIGN # 2 SYSTEM TIMING CONTROLLER PATTERN Z80-1 REVISION A AUTHOR TIM OLMSTEAD COMPANY DATE 09/21/96 CHIP PAL1 PAL16L8 ;---------------------------------- PIN Declarations --------------- PIN 1 MREQ ; INPUT PIN 2 CASIN ; INPUT PIN 3 A07 ; INPUT PIN 4 A06 ; INPUT PIN 5 RD ; INPUT PIN 6 IORQ ; INPUT PIN 7 M1 ; INPUT PIN 8 RFSH ; INPUT PIN 9 WR ; INPUT PIN 10 GND ; INPUT PIN 11 PIN11 ; INPUT PIN 12 CAS COMBINATORIAL ; OUTPUT PIN 13 RAS COMBINATORIAL ; OUTPUT PIN 14 STARTUP ; INPUT PIN 15 EN245 COMBINATORIAL ; OUTPUT PIN 16 CTC COMBINATORIAL ; OUTPUT PIN 17 SIO COMBINATORIAL ; OUTPUT PIN 18 ROM COMBINATORIAL ; OUTPUT PIN 19 RAMSEL COMBINATORIAL ; OUTPUT PIN 20 VCC ; INPUT ;----------------------------------- Boolean Equation Segment ------ EQUATIONS /RAMSEL = /MREQ * RFSH ; THE WHOLE 64K IS DRAM /EN245 = /MREQ * /STARTUP * /RD ; ENABLE 245 FOR READS ONLY /ROM = STARTUP * /MREQ * /RD ; ROM IS ONLY ENABLED DURING STARTUP /RAS = /MREQ * STARTUP * /WR * RFSH ; ONLY DO WRITES DURING STARTUP + /MREQ * /STARTUP * RFSH ; ALL ACCESSES AFTER STARTUP + /MREQ * /RFSH ; REFRESH IS RAS ONLY /CAS = RFSH * /CASIN * /RD * /STARTUP ; NORMAL CAS FOR MEMORY READ AFTER ; STARTUP + RFSH * /CASIN * /WR ; HOLD OFF CAS FOR EARLY WRITES /SIO = /IORQ * M1 * /A07 * /A06 ; SIO AT 00H /CTC = /IORQ * M1 * /A07 * A06 ; CTC AT 40H