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CIRCUIT 3

Our third design attempt will again be a Z80 running at 4 MHz, and having 64K of dynamic memory. It is the same as the second example except that we have implemented the RAS ONLY refresh the hard way. This example is really for the reader who may NOT be using a Zilog processor. It would be hard to justify using external refresh counters, and the extra level of multiplexers, for a Zilog processor. The Z80, Z180, Z280, Z380, and Z8000 all have refresh capabilities.

Again on page 2 we see the heart of the DRAM design. This time it looks quite different. The first thing we notice is a second level of multipexers. Our normal address multiplexers feed a second set of 74157's. These new multiplexers are configured to normally pass the data on their "B" inputs through. This will present the normal addresses to the memories. The select pins of these new multiplexers is driven by RFSH* from the Z80. During a refresh cycle this signal will go low, and select the "A" inouts of the multiplexers. This gates the outputs of an eight bit counter through to the DRAMs.

The 74LS393 counter is incremented on the high to low transition of its' clock, so RFSH is inverted to drive the first section. The counter is incremented at the end of the refresh cycle. It will continue to increment for every refresh cycle. This will meet the needs of our dynamic memories. To refresh larger memories you would need more bits on the counter, and wider multiplexers.

NOTE : The PAL listing for this design is included for completeness, but it is identical to design example 2.

/* Also: CKT3.PDS and compiled JEDEC: CKT3.JED */

;PALASM Design Description
;---------------------------------- Declaration Segment ------------
TITLE    SAMPLE Z80 DESIGN # 3 SYSTEM TIMING CONTROLLER
PATTERN  Z80-1
REVISION A
AUTHOR   TIM OLMSTEAD
COMPANY  
DATE     09/21/96
CHIP     PAL1  PAL16L8
;---------------------------------- PIN Declarations ---------------
PIN  1          MREQ                            ; INPUT 
PIN  2          CASIN                           ; INPUT 
PIN  3          A07                             ; INPUT 
PIN  4          A06                             ; INPUT 
PIN  5          RD                              ; INPUT 
PIN  6          IORQ                            ; INPUT 
PIN  7          M1                              ; INPUT 
PIN  8          RFSH                            ; INPUT 
PIN  9          WR                              ; INPUT 
PIN  10         GND                             ; INPUT 
PIN  11         PIN11                           ; INPUT 
PIN  12         CAS                  COMBINATORIAL ; OUTPUT
PIN  13         RAS                  COMBINATORIAL ; OUTPUT
PIN  14         STARTUP                         ; INPUT 
PIN  15         EN245                COMBINATORIAL ; OUTPUT
PIN  16         CTC                  COMBINATORIAL ; OUTPUT
PIN  17         SIO                  COMBINATORIAL ; OUTPUT
PIN  18         ROM                  COMBINATORIAL ; OUTPUT
PIN  19         RAMSEL               COMBINATORIAL ; OUTPUT
PIN  20         VCC                             ; INPUT 
;----------------------------------- Boolean Equation Segment ------
EQUATIONS

/RAMSEL = /MREQ * RFSH           ; THE WHOLE 64K IS DRAM

/EN245 = /MREQ * /STARTUP * /RD  ; ENABLE 245 FOR READS ONLY

/ROM = STARTUP * /MREQ * /RD     ; ROM IS ONLY ENABLED DURING STARTUP

/RAS = /MREQ * STARTUP * /WR * RFSH ; ONLY DO WRITES DURING STARTUP
     + /MREQ * /STARTUP * RFSH   ; ALL ACCESSES AFTER STARTUP
     + /MREQ * /RFSH             ; REFRESH IS RAS ONLY

/CAS = RFSH * /CASIN * /RD * /STARTUP ; NORMAL CAS FOR MEMORY READ AFTER
                                      ; STARTUP
     + RFSH * /CASIN * /WR       ; HOLD OFF CAS FOR EARLY WRITES

/SIO = /IORQ * M1 * /A07 * /A06  ; SIO AT 00H

/CTC = /IORQ * M1 * /A07 * A06   ; CTC AT 40H



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