;PALASM Design Description ;---------------------------------- Declaration Segment ------------ TITLE SAMPLE Z80 DESIGN # 2 SYSTEM TIMING CONTROLLER PATTERN Z80-1 REVISION A AUTHOR TIM OLMSTEAD COMPANY DATE 09/21/96 CHIP PAL1 PAL16L8 ;---------------------------------- PIN Declarations --------------- PIN 1 MREQ ; INPUT PIN 2 CASIN ; INPUT PIN 3 A07 ; INPUT PIN 4 A06 ; INPUT PIN 5 RD ; INPUT PIN 6 IORQ ; INPUT PIN 7 M1 ; INPUT PIN 8 RFSH ; INPUT PIN 9 WR ; INPUT PIN 10 GND ; INPUT PIN 11 PIN11 ; INPUT PIN 12 CAS COMBINATORIAL ; OUTPUT PIN 13 RAS COMBINATORIAL ; OUTPUT PIN 14 STARTUP ; INPUT PIN 15 EN245 COMBINATORIAL ; OUTPUT PIN 16 CTC COMBINATORIAL ; OUTPUT PIN 17 SIO COMBINATORIAL ; OUTPUT PIN 18 ROM COMBINATORIAL ; OUTPUT PIN 19 RAMSEL COMBINATORIAL ; OUTPUT PIN 20 VCC ; INPUT ;----------------------------------- Boolean Equation Segment ------ EQUATIONS /RAMSEL = /MREQ * RFSH ; THE WHOLE 64K IS DRAM + /MREQ * /RFSH ; REFRESH /EN245 = /MREQ * /STARTUP * /RD ; ENABLE 245 FOR READS ONLY /ROM = STARTUP * /MREQ * /RD ; ROM IS ONLY ENABLED DURING STARTUP /RAS = /MREQ * STARTUP * /WR * RFSH ; ONLY DO WRITES DURING STARTUP + /MREQ * /STARTUP * RFSH ; ALL ACCESSES AFTER STARTUP + /MREQ * /RFSH ; REFRESH IS RAS ONLY /CAS = RFSH * /CASIN * /RD * /STARTUP ; NORMAL CAS FOR MEMORY READ AFTER ; STARTUP + RFSH * /CASIN * /WR ; HOLD OFF CAS FOR EARLY WRITES /SIO = /IORQ * M1 * /A07 * /A06 ; SIO AT 00H /CTC = /IORQ * M1 * /A07 * A06 ; CTC AT 40H
file: /Techref/mem/dram/ckt2.pds, 2KB, , updated: 1996/9/21 14:02, local time: 2024/8/14 21:20,
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