[Menu]>[CPLD]>[4 x 4 selector]


Source code and Explanation
for 4bits x 4channels Selector



001
002
003
004
005
006
007
008
009
010
011
012
013
014
015
016
017
018
019
020
021
022
023
024
025
026
027
028
029
030
031
032
033
034
--******************************************************************************
--*                                                                            *
--*                              4 x 4 selector                                *
--*                                                     Device : XC9536-PC44   *
--*                                                     Author : Seiichi Inoue *
--******************************************************************************

library ieee;                                    -- Defines std_logic types
use ieee.std_logic_1164.all;

entity Selector1 is
  port ( A, B, C, D : in std_logic_vector(3 downto 0); -- Defines ports
         Q : out std_logic_vector(3 downto 0);
         SEL : in std_logic_vector(1 downto 0));      
end;

architecture Selector1_arch of Selector1 is
begin
  process( SEL ) begin
    if SEL = "00" then
      Q <= A;                                    -- SEL=00  A -> OUT
    elsif SEL = "01" then
      Q <= B;                                    -- SEL=01  B -> OUT
    elsif SEL = "10" then
      Q <= C;                                    -- SEL=10  C -> OUT
    else
      Q <= D;                                    -- SEL=11  D -> OUT
    end if;
  end process;
end Selector1_arch;

--******************************************************************************
--*                           end of 4 x 4 selector                            *
--******************************************************************************



Explanation
Line #Comment
009The std_logic library is specified.
012
-014
The pins of the input/output are specified.
020Selection signal(SEL)=00 is judged.
021In case of SEL=00, the input of the A channel is output and logic is completed.
022Selection signal(SEL)=01 is judged.
023In case of SEL=01, the input of the B channel is output and logic is completed.
024Selection signal(SEL)=10 is judged.
025In case of SEL=10, the input of the C channel is output and logic is completed.
027SEL is in the case except the above(SEL=11), the input of the D channel is output and logic is completed.