Logic Familys

Also:

[begin-quote]

Logic Family Choices

With about 20 logic families now extant, some comments are in order about which to use for teaching lab excercises and projects. You are aware, I sincerely hope, that Morse Teaching Center policy is to simplify ordering and to lessen confusion among TAs and students by insisting on close adherence to a set of Recommended Parts. To be sure, such a list will never be complete, so we are willing to expand it as your needs evolve, but the process should be governed by informed choice. We don't want our lab activities to become historic restoration projects.

This first figure comes from a Texas Instruments promotional brochure but is a convenient way of showing most (not all) logic families and where they fit generationally. The original TTL family (e.g. 7400, 7493) had its heyday 20 years ago and is thoroughly obsolete. One of its prominent successors, the 74ALSxxx family, is still quite current and readily available.

But with CMOS becoming the hugely dominant force in logic integration, this is what we should expose students to. The best choice for general logic experiments and design is the 74HCxxx family. So the modern 74HC76 will be a supply-voltage (+5V) and pin-compatible dual flip-flop like the old 7476. For those interested in more details, the electrical characteristics of the major families are in Table 9.1 (pictured below) from Horowitz & Hill "The Art of Electronics," with much additional information in the rest of chapt. 9

Not all logic functions you might will be available in the modern HC and HCT families, especially when it comes to specialized interface functions like display drivers. In those cases we need to resort to ALS or even LS. But always please consider if redesign can bring your logic needs into the HC family. When a design has to mix logic families, some care may be indicated as per the interconnection guidelines in Horowitz & Hill Table 9.2. (pictured below)

Lou Berman and I are ready to work with you on clarifying any particulars of logic IC (and other component) choices, to bring them into harmony with, and constructively evolve, our " Recommended Parts" library.

TABLE 9.1. -- LOGIC FAMILIES

t_pd(’00)
(C_L=50pF)

P_diss

V_supply

f_clk(’74)

(C_L=0)

I_OL

I_IL

V_th

Date

Family

typ
(ns)

max
(ns)

max
(MHz)

@1MHz
(mW/gate)

@0.5V max
(mA)

max
(mA)

typ
(V)

min
(V)

nom
(V)

max
(V)

of intro

CMOS

AC
ACT

5.1

125

0.5

V₊/2
1.4

2
4.5

5 or 3.3
5

6
5.5

1985

HC
HCT

0.5

V₊/2
1.4

2
4.5

5
5

6
5.5

1982

4000B/74C

@10V
@5V

30
50

60
90

5
2

1.2
0.3

1.3
0.5

0
0

V₊/2

5-15

1970

TTL

4.5

105

0.5

1.5

4.5

5.5

1980

3.5

100

5.4

0.6

1.6

4.75

5.25

1979

ALS

1.3

0.1

1.4

4.5

5.5

1980

0.4

1.1

4.75

5.25

1976

TABLE 9.2. -- LOGIC FAMILIES CONNECTIONS

TO *FROM*	TTL	HCT ACT	HC AC	HC, AC @3.3V	NMOS LSI	4000B, 74C @5V	4000B, 74C @10V
TTL	OK	OK	A	OK	OK	A	B
HCT ACT	OK	OK	OK	NO	OK	OK	B
HC AC	OK	OK	OK	NO	OK	OK	B
HC, AC @3.3V	OK	OK	NO	OK	OK	B	B
NMOS LSI	OK	OK	A	OK	OK	A	B
4000B, 74C @5V	OK^a	OK	OK	NO	OK	OK	B
4000B, 74C @10V	C	C	C	C	C	C	OK

^(a) with limited fanout.

A - pullup to +5V, or use HCT as interface.

B - use i)OC pullup to +10V, or ii)40109, 14504, or LTC1045 level translator.

C - use 74C901/2, 4049/50, 14504, or LTC1045 level translator.

[end-quote -- from http://www.eng.yale.edu/ee-labs/morse/main.htm ]

Questions:

KILLspamankit_83saxena at yahoo.com asks: " What is the logic level assumed at the hanging input of CMOS logic device?" James Newton replies: What do you mean by "hanging input"?+
+ Does the Unused Pins FAQ answer your question?
OK, this is the most obscure logic question, a challenge to you a supposed brilliant engineer. I have an application which uses a bi-lateral switch (HEF4066BP). How can I have a high input impedance (low conducting state), when the HEF4066BP has no power supply? In other words I can still drive a signal through the 4066, when it has no power attached. Is there a logic family which has a different intrinsic circuitry, which stops this?
So you want to drive an active signal to an unpowered chip, and you *don't* want to see any of the signal on the output? The datasheet refers to the HEF family specifications . The family specs mention an Absolute Maximum rating of Vin in the range -0.5 V to Vdd+0.5 V. If the signal is more than +-0.5 V when you feed it to the chip, this is outside the chip's rating, and it will likely permanently damage the chip (by melting the input protection diodes and in other ways).
Most other logic families have similar absolute maximum ratings. Even if your signal is within that range, most logic chips aren't really specified as to their characteristics when the power is off. Perhaps it would be best to implement this sort of thing using something other than a logic chip.
I'm pretty sure the the H11F1 "photo FET optocoupler" ($1.88 as of 2006-06) plus a resistor would do what you want. Hook the resistor to the power supply to turn on the LED when the power comes on. Hook the input to one pin of the FET (up to +- 30 V). Then the other pin of the FET is completely isolated (300 MOhm) when the power goes off, and connected (200 Ohm) when the power comes on. Tell me if you find any other solutions that are better in any way.
-- David Cary
KILLspamnitin_ndg at yahoo.com asks: " Question: what will happend if i commect signal of 5 MHz out put from CMOS ACT(fmax 125MHz) to in put 4000B (fmax 3MHz) ." James Newton replies: 5Mhz is more than the fMax of 3Mhz. It might work, but would be outside the device spec. and so probably would not work.+
+
KILLspammazher_iqbal at rediffmail.com asks: " which logic family is best and why?" James Newton replies: Before I answer that question, let me just say that the hammer is the best tool. No other tool is better, no matter the application, than the hammer. In every case, where I need a tool, I reach for the hammer. Loosen a bolt? Hammer. Cut wood? Hammer. Milling complex shapes out of metal? Hammer.
Now, about the best logic family: That depends on the application. Each has advantages and disadvantages and you must try to match those to what is important in each specific application.
But when the time comes to insert the IC into the socket? Be sure to use a hammer.+
+
KILLspamX9A3 at Vnet.Net asks:
I have a 74HC02 at Vcc=3.1 V (battery powered switched via a Max6363)with an up level connected to a 74HC00 with Vcc=+5 (V standby in a PC) - The 74HC00 is not powered when the Vsb of the PC is off. The battery powered 74HC02 (in a latch arrangement) senses an event and sets to an up state. When Vsb comes on, the remainder of the circuits work fine. But when shutting the Vsb off, to run on the battery again, the 74HC00 pulls 8 ma or so out of the battery through the 74HC02. How can I interface these two circuits that are using different Vcc's to minimize the current drain?
Thanks ... Dennis Abraham .. Concord, NC
KILLspamsonusmiles at indiatimes.com asks:
i am looking forward for developing a sofrware for "Digital Simulator for Logic Circuit".
Will the choice of "Logic family" i.e. whether i am using TTL , CMOS or any other amke a difference to a "Digital Behaoiur" of the gates ?
Please guide me...

James Newton replies: Yes. The time required for a signal to pass through the gate will be slightly different, and the fan-out, the number of gates that can be driven by one gate, will change.+
+
KILLspamdalem at isco.com asks:
We are using HCT and AHCT parts in a processor buss design. We are seeing various degrees of ringing and overshoot. What is an exceptable amount of this type of effect? It does not seem to be a problem, but how can one reduce the ringing and overshoot.

The only real problems caused by ringing and overshoot are EMI and false or repeated triggering in extreme cases. And higher power consumption to some degree... To reduce:
A) Use a slower, lower power logic family.
B) put a low value resistor in SERIES (not parallel) with each signal. You will see the ringing and overshoot decrease as the resistance is increased. This will also cause the signal transitions to be slower and may (not very likely) make small changes to timing as the resistance becomes too much.
This will also decrease noise in the system and drop power use a little.
+

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Logic Familys

A - Advanced

L - Low

S - Schottky

C - CMOS interface (not necessarily CMOS components but designed for connection to other CMOS devices)

T - TTL interface (not necessarily TTL components but designed for connection to other TTL devices) Devices are assumed to be TTL unless otherwise specified.

F - Fast TTL.

(none) 74xxx TTL Fast, high power, lots of supply noise
(none) 4xxx CMOS slow, low power, low supply noise
L - Low-Power TTL
- LS Low-Power Schottky Logic low speed, low drive, 5 V VCC
- LV Low-Voltage CMOS Technology low speed, low drive
  - LVC
  - LVT
H - High speed TTL (High speed for the time, pretty slow compared to newer types)
- HC - High-Speed CMOS Logic low speed, low drive, 5 V VCC For low-power logic requirements. typical propagation delays of 15.6 ns. 80 µA maximum static current. CMOS-compatible inputs
  - HCT - TTL-compatible inputs.
A - Advanced
- AC - Advanced CMOS. Medium speed, medium drive (24 mA), 5 V VCC
  - ACT - TTL-compatible inputs.
- AHC - Advanced High-Speed CMOS Logic medium speed, low drive, 5 V VCC. For HCMOS users who need more speed for low-power, low-noise, and low-drive applications. typical propagation delays of 5.2 ns (octals), which is about three times faster than HC devices. 40 µA maximum static current, half that of HCMOS. Output-drive current is ±8 mA at 5 V VCC and ±4 mA at 3.3 V VCC. CMOS-compatible inputs
  - AHCT - TTL-compatible inputs.
- AS - Advanced Schottky Logic. medium speed, high drive, 5 V VCC
- ALS - Advanced Low-Power Schottky Logic low speed, high drive, 5 V VCC
F - Fast Schottky. Logic medium speed, high drive, 5 V VCC 74F logic is a general-purpose family of high-speed advanced bipolar logic.

Logic Familys

Logic Family Choices

Logic Familys

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