TI MSP430 Instructions

There are thee general groups of instuctions:
 

Double Operand

12 Op-codes, a Source (S-Reg) with 4 addressing modes specified by As and a Destination (D-Reg) with only 2 modes selected by Ad, (3 if you fake one) as well as a bit called Bw or B/W to select between byte operation and word operations. Those modes start out simple, but some interesting tricks really make them flexable.

Single Operand

7 Op-codes and a destination (D-Reg) with 4 addressing modes specified by Ad which is now 2 bits. And byte or word with Bw

Jumps

7 sorts of PC relative jumps with a 10 bit offset.

Instruction Formats

S-Reg / D-Reg

Source or Destination Register
Can be any of the 16 available registers.
R0 is the Program Counter (PC),
R1 is the Stack Pointer (SP),
R2 is the Status Register but will return special constant values  (see Constant Registers below) as will
R3 which is called the Zero Register but can return 0, 1 or 2 depending on the Source Addressing Mode.

As / Ad

Addressing Modes

In Single Operand instructions, Ad is the two bit value indicating the Destination Addressing Mode and is decoded as per this table, in Double Operand instructions As is the 2 bit Source Addressing Mode value and Ad is a single bit. This single bit selects between Direct or Indexed addressing (again using an immediate number stored after the instruction). Of course, Indirect is easy to fake with a 0 offset in the Indexed address. In the case that both source and destination addresses are Indexed, the immediate value for the source is stored directly after the instruction, followed by the one for the destination address.

Ax	Name	Source	Syntax	Description
00	Direct	Register	Rn	The actual value stored in the register indicated by S-Reg
01	Indexed	Memory pointed to by Register + Immediate Number	n(Rn)	An immediate 16 bit value (stored in the next program word after the instruction) is added to the value in the register.   If the register is R0 (the PC) then we have PC relative addressing. This is how labels are referenced. The assembler will translate &lable into lable(R0)
10	Indirect	Memory pointed to by Register	@Rn	The value in the register is used to index memory and return the value at that addres in memory. In a Double Operand instruction, since there is no Indirect mode for the destination (Ad is only 1 bit, remember), the assembler will translate a destination of @Rn into an Indexed mode reference to 0(Rn)
11	Increment	Memory pointed to by Register (Increment Register)	@Rn+	Just like Indirect but then the register is incremented by 1 for byte or 2 for word depending on Bw. Note: the exception is when the register is the Stack Pointer: Then it is always incremented by 2.   When the register is PC, the source is an immediate value stored after the instruction which will be skipped by the increment! Clever huh? The syntax for that is just #n and the assembler will translate it into @R0+ and put the value of n in the word after the instruction.   The source register is incremented before the destination is computed so if the same register is used as the destination, the source with be based on the original value and the destination on the incremented value.   In a Double Operand instruction, the destination can not be post incremented (Ad is only 1 bit!), only the source. In a Single Operand instuction, Ad is 2 bits, and the destination can be incremented just fine.

D-Reg

Destination Register

Bw

Byte(=1) or Word(=0) operation

Constant Registers

When r2 (the status register) or r3 (the zero register) are specified, the addressing mode bits are decoded specially:

Memory aid: R3 returns a sign extended version of the As mode.

Double Operand group

Instructions

Emulated Group

See:

• http://mspgcc.sourceforge.net/manual/x147.html

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