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Errata

Silicon User Information for the SX18/20/28AC 50 MIPS silicon

Date Code(s): 9849, 9850, 9910A4, 9912B4
1. Parallel and Serial Programming Times
Description: Parallel and serial programming times are 100 msec/word. The spec is 10 msec/word.
Workaround: Adjust programming environment for 100 msec programming time.
Plan: It will be fixed in the future revision of the silicon.
2. Internal RC Oscillator Frequency
Description: The operation frequency of the internal RC oscillator is not 4 MHz. This is due to the fact that SX devices require trimming to obtain 4 MHz operation. The parts shipped out of the factory are not trimmed. Currently, the device relies on the programming tool to provide the trimming. Revision 1.0 and lower revisions of the SX Key does not support trimming.
Workaround: Revision 1.1 of the SX Key provides the trimming capability.
Plan: Programming tools will support trimming. In addition, SX devices will be trimmed at the factory in the future.
3. In-System Programming (ISP) Consideration
Description: Device may draw excessive current during ISP that may cause the device operation to stop and result in potential damage to the OSC1 pin.
Workaround: Use a 100-ohm resistor in series with the OSC1 pin.
Plan: Will be fixed in the future revision of the silicon.


Silicon User Information for the SX48/52BD 50 MIPS silicon

1. Differential Comparator
Description: The comparator has oscillation noise of +- 1V around the threshold voltage.
Workaround: None.
Plan: It will be fixed in the future revision of the silicon.
2. Vdd Range
Description: Vdd range is limited to 4.5V to 5.5V.
Workaround: None.
Plan: It will be fixed in the future revision of the silicon. The new voltage range is expected to be 2.5V to 5.5V.
3. Internal RC Oscillator Frequency Trimming
Description: The default operating frequency of the internal RC oscillator is not 4 MHz. This is due to the fact that SX devices require trimming to obtain 4 MHz operation. The parts shipped out of the factory are not trimmed.
Workaround: The development and programming tools provide the trimming capability.
Plan: The development and programming tools support trimming.

 


Silicon User Information for the 18/20/28 lead 50 MIPS silicon

Date Code(s): 9815, 9818, 9819, 9825, 9827, 9829, 9830, 9837, 9838, 9841, 9843, 9844, 9848, 9908, 9911, 9913
1. Parallel and Serial Programming Times
Description: Parallel and serial programming times are 100 msec/word. The spec is 10 msec/word.
Workaround: Adjust programming environment for 100 msec programming time.
Plan: It will be fixed in the future revision of the silicon.
2. Vdd Range
Description: Vdd range is limited from 4.5V to 6.25V
Workaround: The limitation is due to the Brown Out trip level, which is set to 4.2V. In addition, the programming time is longer at lower voltages. If the Brown Out detector is disabled and the programming time is extended to 1 sec/word, the device can be operated down to 3.3V.
Plan: It will be fixed in the future revision of the silicon.
3. Prescaler Assignment
Description: In Turbo mode, if the Prescaler is not assigned to the RTCC, the RTCC will not sense any external events. If the Prescaler is assigned to the RTCC, the RTCC works as an external event counter. With the Prescaler assigned to the WDT (Watchdog Timer), the RTCC will only function as an internal timer clocked internally and will ignore any external events.
Workaround: None.
Plan: It will be fixed in the future revision of the silicon.
4. Internal RC Oscillator Frequency
Description: The operation frequency of the internal RC oscillator is not 4 MHz. This is due to the fact that SX devices require trimming to obtain 4 MHz operation. The parts shipped out of the factory are not trimmed. Currently, the device relies on the programming tool to provide the trimming. Revision 1.0 and lower revisions of the SX Key does not support trimming.
Workaround: Revision 1.1 of the SX Key provides the trimming capability.
Plan: Programming tools will support trimming. In addition, SX devices will be trimmed at the factory in the future.
5. ESD
Description: All the I/O pins passed 2000V test. Vdd, Vss, OSC1 and OSC2 go up to 1000V.
Workaround: None.
Plan: Will be fixed in the future revision of the silicon.
6. In-System Programming (ISP) Consideration
Description: Device may draw excessive current during ISP that may cause the device operation to stop and result in potential damage to the OSC1 pin.
Workaround: Use a 100-ohm resistor in series with the OSC1 pin.
Plan: Will be fixed in the future revision of the silicon.

Silicon User Information for the 18/20/28 lead 50 MIPS silicon

Date Code(s):
Known Issues: 9747, 9749, 9750, 9810, 9811, 9812
  1. With Vpp > 13V, device will be damaged in both serial and parallel programming modes. Workaround: Avoid applying Vpp > 12.5V, latest version of SX-Key hardware tested at Vpp = 12V (1/22/98). Use 100-ohm resistor in series between OSC1 pin and pin 4 of SX-Key to prevent over voltage condition.
  2. Internal RC operates at 3.2 MHz maximum (not 4 MHz, as per specification).
Workaround: None.
Plan: Will be fixed in Rev. 2.4.
  3. External RC operates from 100kHz to 8MHz maximum.
Plan: Will be fixed in Rev. 2.4.
  4. Power On Reset (POR) will not work if Vdd rise time is slower than expected (100 msec from 0 to 5 V).
Workaround: Vdd rise time needs to be less than 100 mS. If not using ISP, reset FUSEX.7 (BOSC) [device will have higher power consumption, and will not be able to program via ISP].
  5. Parallel and Serial programming times are 100 mS/word (Spec is 10 msec/word).
Workaround: Adjust programming environment for 100msec programming time, fixed TBD.
  6. Vdd range limited from 4.5V to 6.25V.
Plan: Will be fixed in the future revision.
  7. Crystal clock operation range: 4-30 MHz.
Workaround: Use external clock, ceramic resonators or external or internal RC for other clock speeds.
Plan: Will be fixed in Rev. 2.4.
  8. In TURBO mode and if the Prescaler is not assigned to the RTCC, the RTCC will not sense any external events. If the Prescaler is assigned to the RTCC, the counter function works as described. If the Prescaler is assigned to the WDT, then the RTCC will only function as an internal clock timer, but operation as an external event counter is inoperative.
Plan: Will be fixed in the future revision.
  9. Sleep current is 20uA@5V typ., 60uA@5V max.
Plan: Will be fixed in the future revision.
  10. The In-System Debugging (ISD) does not work as described. Plan: Will be fixed in Revision 2.4.

Date Code(s):
Known Issues: 9814, 9818, 9819
  1. Parallel and Serial programming times are 100 msec/word (Specification is for 10 msec/word).
Workaround: Adjust programming environment for 100msec programming time.
Plan: Will be fixed in the future revision.
  2. Vdd range limited from 4.5V to 6.25V.
Plan: Will be fixed in the future revision.
  3. External Crystal requires a feedback resistor in parallel with the crystal, but allows frequency operation from 1MHz to 50MHz.
  4. In TURBO mode and if the Prescaler is not assigned to the RTCC, the RTCC will not sense any external events. If the Prescaler is assigned to the RTCC, the counter function works as described. If the Prescaler is assigned to the WDT, then the RTCC will only function as an internal clock timer, but operation as an external event counter is inoperative.
Plan: Will be fixed in the future revision.
  5. Sleep mode current 60uA@5V max., 20uA@5V typ. Plan: Will be fixed in the future revision.

See also:


file: /Techref/scenix/errata.htm, 11KB, , updated: 2002/11/1 18:08, local time: 2017/11/20 01:49, owner: JMN-EFP-786,
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