>From: "Thomas C. Sefranek" <
.....tcsKILLspam
@spam@CMCORP.COM>
>To:
PICLIST
KILLspamMITVMA.MIT.EDU
>Subject: Re: Vref on PIC 16C74
>Date: Wed, Apr 5, 2000, 12:23 PM
>
> Paul Howell wrote:
>
>> Hi -
>>
>> I'm new to the PICLIST too, so thanks in advance for the help.
>>
>> I am building a programmable high voltage power supply. It charges a
>> capacitor bank that discharges through flash tube (pretty ordinary stuff).
>> What is a little different is that the output must be confined to
>> (logarithmically) equal discrete steps. It works by sensing the voltage
>> output (through a divider) from the power supply compared to a setpoint
>> (from a look-up table) and altering the duty cycle of the power supply to
>> meet the setpoint (hexfet type of approach). There are only 12 steps, and
>> the accuracy and frequency requirements are such that the internal 8 bit A/D
>> is adequate to the task of sensing the divider voltage.
>>
>
> Been there, Done that, Have the tee shirt!
> I built more than an dozen supplies using the 16C73B,
> From as low a 150 volts up to 7.5 kV.
>
>> Everything works just fine, but here's my problem that I thought would be
>> simple. The A/D supposedly has two ways of taking a reference voltage
>> depending on how the register ADCON1 is set. The Vref can either be taken
>> from Vdd, or taken from whatever external voltage is applied to RA3.
>> Naturally, I would like to apply a nice, stable Vref rather than taking Vdd
>> which may (and does) droop internally. Unfortunately, setting the Vref
>> either way seems to make little, if any difference.
>
> Strange...
>
>> I am using a PIC16C74A. I have checked and re-checked my settings. They are
>> as follows: RA0 - RA5 tristated (TRISA set), RA0, RA1, RA2, RA4, RA5 set to
>> analog input, RA3 set to Vref (not Vdd but is seems to make little
>> difference) via ADCON1, and A/D input channel set to RA0 via ADCON0. I am
>> addressing the correct bank when setting these registers. The chip is
>> operating at 20MHz, the A/D clock is set to 32Tosc (1.6uS) . The charging
>> time is regulated by a software timer and is well above the minimum
>> recommended. The analog input is buffered by an op-amp so it has a nice, low
>> impedance. The Vref is buffered too. Conversion is paced by polling the A/D
>> complete flag.
>>
>> To summarize with an example, with Vref set internally to Vdd (5V in my
>> case) one would expect an A/D response of about128/255 on an input of 2.5V,
>> and 255/255 for the same input but with Vref selected and 2.5V applied.
>> Doesn't happen. This is driving me nuts!
>
> What do you mean "Doesn't happen.", what DO you get?
>
>>
>>
>> Thanks Paul Howell
>>
>> Please reply to the PICLIST....
>
> --
> *
> | __O Thomas C. Sefranek
.....tcsKILLspam
.....cmcorp.com
> |_-\<,_ Amateur Radio Operator: WA1RHP
> (*)/ (*) Bicycle mobile on 145.41, 448.625 MHz
>
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