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PICList Thread
'Reading Pot with Sigma Delta - was : What is a Si'
2000\04\17@195406 by Russell McMahon

picon face
>When you are using a pot as a reference then you
>need to account for the fact that the output
>impedance of the pot varies with voltage.


It should be possible to produce an expression that includes the variable
resistance of the POT in calculating the output result. This is continuous
allowing the original setting to be calculated.

Brief example to try to clarify the above.
Vcc=5 volt
Imagine a 10K resistor from the pot wiper to the SD capacitor.
Pot is 10K say
Pot ends go to Vcc and ground.
Micro drives SD cap also with a 10K resistor

When pot is at centre point it looks like a 2.5V source behind a 5k resistor
(Thevanin equivalent)
The SD sees 2.5V behind 15K which LOOKS like 2.5*10/15 = 1.666V behind 10K
so the SD reports a value of 1.666V (if it assumes that a 10K input resistor
is used.

With pot wiper at full supply the SD sees 5v behind 10K and reports 5V

With pot wiper at ground the SD sees 0V behind 10K and reports 0V

With wiper at 25% position from ground the pot looks like Vcc/4 = 1.25V
behind 2.5K//7.5K = 1.875 K
To the Sd this looks like 1.25V behind 11.875K which is the same as 1.053
volt behind 10K so it reports 1.053 volt.

The result of all this is that the pot wiper reads as in the middle when it
is in the middle but appears to approach the ends more rapidly than you
would expect. Certainly reverse engineerable.

Lesee

Pot is set at fraction Position of Pot = X
0 <= X <= 1
Resistor from SD cap to pot wiper = R
Pot Resistance whole  track = P
Pot connects to Vcc and ground

1. Pot effective resistance at wiper is the resistance of the two portions
abvoive and below wiper in parallel =

P.X//P(1-X)
= P.X.P(1-X)/P
= X.P(1-X)

eg at 0.2 of full scale

R effective = 0.2 * P(1-0.2)
= 0.16 of full pot value
ie a 10K pot set to 20% position will have a 1K6 effective resistance.

2. Pot open circuit voltage = Vcc * X

3.    Equivalent resistance for Sd = R + Rpot
= R+ X.P(1-P)

4.    SD sees equivalent voltage of

Vwiper x R/(R + Reffective-pot)

***************************************************************
* SD voltage seen = Vcc * .X  *  R / (X * P * (1-X) + R)  *
***************************************************************
Whereas what it SHOULD see ideally is Vcc * X

Solve for X (a quadratic) and you get X in terms of the SD voltage reported.
Not pretty but workable.

WARNING: I haven't checked my algebra - a slip somewhere is quite likely but
anyone who will or can wade through this should be able to follow the
argument well enough to spot any errors.

ALSO - may have made a/some fundamental wrong assumptions :-)
I have assumed that eg doubling the input resistance will halve the apparent
voltage behind it (and as I recall this is correct but I haven't played with
the theory recently) - if this is NOT correct (but I think it is) then NONE
of the forgoing works ;-)

Now, back to work !!!

regards




     Russell McMahon
_____________________________

- http://www.easttimor.com
      Updated regularly:
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What can one man* do?
Help the hungry at no cost to yourself!
at  http://www.thehungersite.com/

(* - or woman, child or internet enabled intelligent entity :-))


{Original Message removed}

2000\04\17@224658 by Russell McMahon

picon face
Alice,

It should NEVER hang if designed correctly.
In a correctly designed SD converter the processor should always be able to
"counteract" any input supplied by the the "user". In typical uP solutions
the uP swings a pin between Vcc rail  and ground to drive the SD cap and the
cap is held at about half rail by the SD loop (assuming a CMOS cpu and a
transition point at about half supply.


As long as your input can never go outside supply rails and your input
resistor is at least as large (or just slightly larger) than the feedback
resistor being driven by the uP it should never hang.

Aha.
You may be connecting pot wiper directly to the SD cap - at ends of its
travel the pot resistance approaches zero ohms and the SAD cannot drive it.
This arrangement should work.

- SD integrator cap, one side to ground
- Feedback R from uP{ feedback pin to top of SD cap.
- Pot with top of track to Vcc
- Bottom of pot track to ground.
- R from pot wiper same size as feedback R PLUS a small amount extra.

eg Say feedback R is 10 K make series R from pot wiper 12K

This will be non-linear above and below middle as per my prior post but
should NEVER hang.
Adding a very large cap to the pot wiper should reduce the non-linearity. A
large enough cap should mean the pot R can be ignored.
An opamp looks like a VERY large cap :-)
In my necessarily low cost design I am using 10k resistors, a 1uF
integrating cap (non-polar) and an LM324 to drive the input R.

Added complications probably not needed here: I add a positive bias to the
input signal and have a 2K7 to ground from the '324 output which persuades
the LM324 to always source current through its upper pass transistors - the
amount sourced varies.
I use a large cap (1uF) and small R's (10k) for reasons specific to my
application and not necessarily applicable to SDs in general. It works.

In my system I initially ramp the SD cap up to the operating point and then
hold it there constantly using a timer interupt driven code (also used for
other things). When I want to use the SD converter it is always ready and I
just zero a "high" and "total" counter and wait for N interrupts then  read
the SD result. The longer I wait, the more accurate the result (within
reason). I run it at 100uS per sample which is slower than ideal but fits in
with the rest of the system.


Here's the interrupt driven part of my SD
This is Z8 but probably easy enough to read.


** PICLIST COMMENTS HAVE ** IN FRONT

** 1st portion of loop MUST be isochronous - ie all paths must have same
length.

; ++++++++ SD Tracking +++++++++++++++++++++++
; - SD input / output tracking
; NB this part of SD is NOT turned off by FSDCountEnable
;    Set output to complement of input

;      Mirror Input

** VITAL to read ONCE per cycle only

       LD      ShadowBIn, PTBIN    ; Snapshot SD Input

       TCM     ShadowBIn, #PB_SDIn ; #010h    ; If Comparator is high
       JR      EQ, ICompHi         ; then goto high processing

;     Comparator is low so set output high

       OR      ShadowAOut, #PAO_POS ; - MPWMHigh
       JR      ICompSet

ICompHi ; comparator is high so set output low

       AND     ShadowAOut, #FLIP^PAO_POS ; debug db8 - MPWMLow
       NOP     ; debug 000127 - isochronous post irq path to SD output.

ICompSet

;    Control Output.

       LD      PTAOut, ShadowAOut           ; Set output

; - End of basic SD tracking code

** The above makes the cap track permanently.
** Following code is only needed when SD is in use.


; ++++ SD Counter Processing +++++++++++++++++++++++++++
;
; - Now optionally do SD counter processing:

       TM      RFlags, #FSDCountEnable   ; IF enable not set
       JR      EQ, INoSDCnt                ; then bypass SD downcount
routines.

;     Here if SD count is enabled

;       If input low, inc Low_Counter

       TCM     ShadowBIn, #PB_SDIn ; #010h        ; Test input and if high
       JR      ne, INotLow     ; .DBAD10 ; EQ, INotLow             ; j &
don't increment counter .

** This is the actual SD result

       incw    SDLowCnt              ; else inc low counter

INotLow

;     Decrement Total_Counter
;     and If finished set flag

       DECW    SDTotalCounter    ;
       JR      NZ, DoMoreSD    ;

** Flag is set when requested counts are completed
** Background reads this flag

       OR      RFlags, #FSDDone
       AND     RFlags, #FLIP^FSDCountEnable


DoMoreSD

INoSDCnt


     Russell McMahon
_____________________________

- http://www.easttimor.com
      Updated regularly:
      100,000 refugees STILL in  West Timor face starvation!

- http://www.sudan.com
   And you think Kosovo and Chechnya are bad!

What can one man* do?
Help the hungry at no cost to yourself!
at  http://www.thehungersite.com/

(* - or woman, child or internet enabled intelligent entity :-))


{Original Message removed}

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