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PICList Thread
'RAM Buffer'
1998\04\03@091758 by Robert & Susan Hoar

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Try Ramtron's FM24C04. It is a non-volatile EEPROM which uses ferroelectric
cells.
It has a deep write buffer, which means that it automatically
autoincrements the write address. Therefore it only needs two wire (I2C)
interface to your pic.
Plus since it is ferro, it can have over a billion writes!

Hope this helps anyone out there.
Red
Robert Hoar

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1998\04\03@125030 by SHAWN ELLIS

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> Try Ramtron's FM24C04. It is a non-volatile EEPROM which uses ferroelectric
> cells.
> It has a deep write buffer, which means that it automatically
> autoincrements the write address. Therefore it only needs two wire (I2C)
> interface to your pic.
> Plus since it is ferro, it can have over a billion writes!
>
Well, they don't seem to make one big enough for me.  I need at LEAST
256 KB.

Isn't there a chip out there that will control regular, PC 72-pin RAM
for me?  You know, handle the refresh and chip muxing?

Thanks,

1998\04\03@134831 by Mike Keitz

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On Fri, 3 Apr 1998 12:47:36 EST5EDT SHAWN ELLIS <spespamKILLspamMERC.RX.UGA.EDU>
writes:

>Isn't there a chip out there that will control regular, PC 72-pin RAM
>for me?  You know, handle the refresh and chip muxing?

Umm, a PIC chip maybe?  Oh wait, too complicated.  It can be done though.
You'd connect some of the 32 data lines in parallel so the SIMM acts
like 2 or 4 "narrower" memories of 16 or 8 bits.  Then use decoders (or
extra PIC pins) to CAS only one or two of the 4 banks in the SIMM at once
so the data doesn't conflict.   The PIC would still need to supply 9 or
10 bits of multiplexed address though.

If you only need 2 MB and cost isn't a problem, use 4x 512 Kx8 SRAMs.
Control the SRAM address with a counter (e.g. 2x 74HC4040 gives a 24 bit
binary count, enough to address 16M locations).  Some of the counter bits
(traditionally the higher-order ones) would be decoded to the chip select
pins on the SRAMs so only one chip (for 8-bit bus) or pair of chips (for
16-bit bus) is active at a time.

I assume from the other post that the device has 2 modes of operation:
"acquire" (ADC -> RAM) and "download" (RAM -> RS232) and that both
operations don't have to happen at the same time.  So a simple address
counter is ideal as a single PIC pin can reset it to zero at the start of
each mode.  Another PIC pin would advance the count after each read or
write.  The highest address in use would be stored in PIC RAM and an
internal counter in the PIC would track the external count to tell when
all data has been collected or sent.

The data lines of the RAM would just connect directly to the data lines I
assume already exist from the ADC(s) to the PIC, so no more pins would be
needed for data.  The output-enables on each deevice would control the
direction of data on the 8 or 16-bit bus.  I'd use an 8-bit bus if the
ADCs allow it (have a "byte select" or dual output enables to send only 8
bits at a time) since the speed is so low there's no advantage to a wider
bus.  This will free up 8 PIC pins.  The data bus doesn't even have to be
connected to the PIC at all except to read for RS-232, a parallel->serial
shift register could be connected to shift the data in on one pin.  With
a 40-pin PIC, such measures shouldn't be needed.

Running two or more ADCs would be no problem, just connect them to the
data bus and run the chip selects individually back to the PIC.  The PIC
software would read and store one ADC, then select the other one, read
and store it.  The readings would end up interleaved in the RAM.  If
you're really short on PIC pins, the low order RAM address from the
counter could even be decoded to select an ADC.  But then it wouldn't be
possible to do things like sample only one ADC and fit twice as many
samples in RAM.


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1998\04\03@143842 by SHAWN ELLIS

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>
> >Isn't there a chip out there that will control regular, PC 72-pin RAM
> >for me?  You know, handle the refresh and chip muxing?
>
> Umm, a PIC chip maybe?  Oh wait, too complicated.  It can be done though.
>  You'd connect some of the 32 data lines in parallel so the SIMM acts
> like 2 or 4 "narrower" memories of 16 or 8 bits.  Then use decoders (or
> extra PIC pins) to CAS only one or two of the 4 banks in the SIMM at once
> so the data doesn't conflict.   The PIC would still need to supply 9 or
> 10 bits of multiplexed address though.
>
> If you only need 2 MB and cost isn't a problem, use 4x 512 Kx8 SRAMs.
> Control the SRAM address with a counter (e.g. 2x 74HC4040 gives a 24 bit
> binary count, enough to address 16M locations).  Some of the counter bits
> (traditionally the higher-order ones) would be decoded to the chip select
> pins on the SRAMs so only one chip (for 8-bit bus) or pair of chips (for
> 16-bit bus) is active at a time.
>
Hmmm, this is a intrigueing suggestion.  So, by using your counter
chip, I can use regular SIMM's and only use 8 I/O lines?  Or are you
talking SRAM chips?  I'd like to be able to use a regular SIMM or
DIMM.

> I assume from the other post that the device has 2 modes of operation:
> "acquire" (ADC -> RAM) and "download" (RAM -> RS232) and that both
> operations don't have to happen at the same time.  So a simple address
> counter is ideal as a single PIC pin can reset it to zero at the start of
> each mode.  Another PIC pin would advance the count after each read or
> write.  The highest address in use would be stored in PIC RAM and an
> internal counter in the PIC would track the external count to tell when
> all data has been collected or sent.
>
This would work just fine.

{Quote hidden}

Yeah, that sounds good.

> Running two or more ADCs would be no problem, just connect them to the
> data bus and run the chip selects individually back to the PIC.  The PIC
> software would read and store one ADC, then select the other one, read
> and store it.  The readings would end up interleaved in the RAM.  If
> you're really short on PIC pins, the low order RAM address from the
> counter could even be decoded to select an ADC.  But then it wouldn't be
> possible to do things like sample only one ADC and fit twice as many
> samples in RAM.
>
>
I don't think so, what you described above should leave enough I/O's
free...

This is a really good e-mail.  I have a couple of questions about it
though...

1.  What part's are you referring to me using with the counter chip?
(part no, brand, etc..)

2.  How will I keep the SRAM refreshed?  Or do I not need to worry
abou that?

Thanks so much for your award-winning reply!

1998\04\03@182450 by William Chops Westfield

face picon face
Signetics/Phillips had an AP-note some time ago using an 80451 as a
printer buffer.  the interesting bit was that they used a SIMM as the
buffer, and drove the address lines directly from the micro, doing
RAS, CAS, refresh, and etc all in software...

BillW

1998\04\03@201844 by William Cornutt

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The origional Apple computer had a neat trick with dynamic ram.

The video was stored in the dram in such an order so as they addressed concescive characters to display them, they were also refreshing the dram.

It may be possible to set up the address lines to the dram so that as you put your data in to it, and take the data out (of concective address) you are also hitting the right lines to keep it refreshed.

The only draw back is that after the data is written to the dram, the dram must still be adddressed at the same rate in order to keep it valid.  And then as it is read, the dram will be refreshed by the concetive read.  After the read, there is no need to keep refreshing the dram.

**************************************************

Bill C.     .....wcornuttKILLspamspam.....slip.net

The speculative check instruction must be separate
>from the speculative load because the CPU can't
always determine the validity of the data when
speculatively loading it from memory.
         BYTE  March 1998

**************************************************

----------
>
> Signetics/Phillips had an AP-note some time ago using an 80451 as a
> printer buffer.  the interesting bit was that they used a SIMM as the
> buffer, and drove the address lines directly from the micro, doing
> RAS, CAS, refresh, and etc all in software...
>
> BillW
>

1998\04\03@233416 by Don McKenzie

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William Chops Westfield wrote:
>
> Signetics/Phillips had an AP-note some time ago using an 80451 as a
> printer buffer.  the interesting bit was that they used a SIMM as the
> buffer, and drove the address lines directly from the micro, doing
> RAS, CAS, refresh, and etc all in software...
> BillW

I did a printer buffer some time ago with a Z80 that addressed from 8K
to 4Mb in Dram dips, simms, or combinations thereof. It is all done with
software and has only a 74LS00 and a 74LS04 to hardware interface to the
Drams. I figured I could use the Z80 to address 64Mb before I needed any
additional address decoding logic.

My full source code and schematics in PDF format can be found at:
Don's Download Dungeon http://www.dontronics.com/download.html
I hope someone can learn something from this now dated project.

This was in the days when I could really remember that I wrote software,
and knew when it was bed time as the sun came up to tell me. I gave that
all up. I rise with the sun now. :-)

(Countries that don't have sun, please delete the last sentence.)

Don McKenzie  EraseMEdonspam_OUTspamTakeThisOuTdontronics.com   http://www.dontronics.com

For more details, send a blank message to infospamspam_OUTdontronics.com
or @spam@simstickKILLspamspamdontronics.com or KILLspambasicsKILLspamspamdontronics.com

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