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PICList Thread
'Problems with code in page 1'
1998\03\17@041245 by Darryl Masters

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Hi All,


I am having a problem with running code in page 1 of a PIC16C73A. Below I have
tried to show the structure of my problem code. The code has a timer running
which periodically causes an interrupt. The interrupt service routine is in
page 0. The main code loop has a call to one routine in page 1. The problem is
that the interrupts stop but the main loop continues to function. This only
happens when there is a call to the subroutine in page 1. If I move the
subroutine to page 0 the problem goes away. I think that the problem only
happens when an interrupt has gone off while executing the subroutine. The
subroutine has been reduced to a return statement.



;Page 0

intsr:  save W reg
       save status
       save pclath

       clear ints
       reset timer

       restore pclath
       restore status
       restore w reg
       retfie


main:   loads of stuff

       MOVF    PCLATH,W                ;SAVE CURRENT PCLATH
       MOVWF   TMPREG
       MOVLW   HIGH SUBROUTINE         ;SET PCLATH FOR CALL
       MOVWF   PCLATH
       CALL    SUBROUTINE
       MOVF    TMPREG,W                ;RESETORE OLD PCLATH
       MOVWF   PCLATH

       loads more stuff

       GOTO    main

;page 1
       org     0800

SUBROUTINE:

       loads of subroutine stuff

       RETURN


Any info or ideas to try would be gratefully recieved.

TIA

- Darryl Masters
- spam_OUTdarrylTakeThisOuTspambendix.demon.co.uk

1998\03\17@054420 by Andrew Warren

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Darryl Masters <.....PICLISTKILLspamspam@spam@MITVMA.MIT.EDU> wrote:

> I am having a problem with running code in page 1 of a PIC16C73A.
> ....
>
> intsr:  save W reg
>         save status
>         save pclath
>
>         clear ints
>         reset timer
>
>         restore pclath
>         restore status
>         restore w reg
>         retfie
>
> [etc...]

   Darryl:

   The problem's undoubtedly in your interrupt handler's
   save/restore code.  If you post a copy of the actual "intsr"
   routine, I'm sure that someone here will solve your problem
   immediately.

   -Andy

=== Andrew Warren - fastfwdspamKILLspamix.netcom.com
=== Fast Forward Engineering - Vista, California
=== http://www.geocities.com/SiliconValley/2499

1998\03\17@055722 by Ints Mikelsons

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Better send me programm code which handle interrupts. I think problem is
there.

1998\03\17@142840 by Mike Keitz

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On Tue, 17 Mar 1998 01:50:17 -0800 Andrew Warren <.....fastfwdKILLspamspam.....IX.NETCOM.COM>
writes:
>Darryl Masters <EraseMEPICLISTspam_OUTspamTakeThisOuTMITVMA.MIT.EDU> wrote:
>
>> I am having a problem with running code in page 1 of a PIC16C73A.
>> ....

>    The problem's undoubtedly in your interrupt handler's
>    save/restore code.  If you post a copy of the actual "intsr"
>    routine, I'm sure that someone here will solve your problem
>    immediately.
>
If you can write your ISR without using CALL or GOTO statements (and of
course no modify PCL's either), then there's no need to do anything about
PCLATH at all during the ISR.  Otherwise you'd have to save it and set it
to 0 before the first GOTO or CALL in the ISR.  Another technique is to
write the ISR routines as a macro and place it at the same place in all
(both) code pages.  Then regardless of the value of PCLATH, one or the
other identical copies of code will execute.

In the main program, you don't need to save PCLATH in RAM, just use
bcf/bsf instructions on bit 3 depending on whether the program is going
to page 0 or 1.  This works on chips with 4K (2 pages) of code space.
Larger chips would need to set up higher bits of PCLATH as well.


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1998\03\18@090155 by

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Am I correct in assuming that if you write code that is greater that 1
page, then you must duplicate the ISR in both pages anyway - regardless
of whether my ISR changes PCLATH.

Presumably, if an interrupt occurs whilst executing code in page 1, the
jump vector at 0004h will jump to that location in the CURRENT page - not
page 0.

Therefore ISR _MUST_ exist in both pages(?)

I don't remember this being made clear in the data book regarding
interrupts.... It seems obvious, or am I missing something??? ( I can't
offhand remember how many address bits are in a 'goto' instruction! )

I'm basing these musings on a 16C74 - but it should apply for any
processor.

Neil
----------
From:  Mike Keitz
Sent:  17 March 1998 16:25
To:  PICLISTspamspam_OUTMITVMA.MIT.EDU
Subject:  Re: Problems with code in page 1

On Tue, 17 Mar 1998 01:50:17 -0800 Andrew Warren <@spam@fastfwdKILLspamspamIX.NETCOM.COM>
writes:
{Quote hidden}

If you can write your ISR without using CALL or GOTO statements (and of
course no modify PCL's either), then there's no need to do anything about
PCLATH at all during the ISR.  Otherwise you'd have to save it and set it
to 0 before the first GOTO or CALL in the ISR.  Another technique is to
write the ISR routines as a macro and place it at the same place in all
(both) code pages.  Then regardless of the value of PCLATH, one or the
other identical copies of code will execute.

In the main program, you don't need to save PCLATH in RAM, just use
bcf/bsf instructions on bit 3 depending on whether the program is going
to page 0 or 1.  This works on chips with 4K (2 pages) of code space.
Larger chips would need to set up higher bits of PCLATH as well.


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1998\03\18@105836 by Bob Smith x31105

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> Am I correct in assuming that if you write code that is greater that 1
> page, then you must duplicate the ISR in both pages anyway - regardless
> of whether my ISR changes PCLATH.

my experience - as limited as it is at the moment - is that having the
ISR in page 0 seems to be ok - but I ran into needing to not only save
PCLATH and clearing bit 3, but I had to save STATUS and clear the RP0 bit
as well - which was kind of a trick until I discovered that I could use
FSR for STATUS storage since FSR appears in both pages...

1998\03\18@105838 by Bob Fehrenbach

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"STRONG, Neil -Syntegra" wrote:
>Am I correct in assuming that if you write code that is greater that 1
>page, then you must duplicate the ISR in both pages anyway - regardless
>of whether my ISR changes PCLATH.

No, you only need one copy of the ISR.  If your background is in page 1
when you get an interrupt, execution is vectored to h'0004'.

What you need to avoid is a GOTO ISR instruction at address h'0004'.  A
goto instruction at that location will put you back to page 1.  Locate
the start of your ISR at h'0004', save and restore context as has been
previously described and you should have no problems.

If your ISR has no calls or gotos you can get away without saving PCLATH
but I would regard this as poor practice.  You may make an 'improvement'
later on and forget to add the instructions to save PCLATH.

--
Bob Fehrenbach    Wauwatosa, WI     RemoveMEbfehrenbTakeThisOuTspamexecpc.com

1998\03\18@122134 by Mike Keitz

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On Wed, 18 Mar 1998 08:44:00 PST "STRONG, Neil -Syntegra"
<spamBeGoneSTRONGNspamBeGonespamNEWCASTLE2.SYNTEGRA.AGW.BT.CO.UK> writes:
>Am I correct in assuming that if you write code that is greater that 1
>page, then you must duplicate the ISR in both pages anyway -
>regardless
>of whether my ISR changes PCLATH.
>
>Presumably, if an interrupt occurs whilst executing code in page 1,
>the
>jump vector at 0004h will jump to that location in the CURRENT page -
>not
>page 0.
>
>Therefore ISR _MUST_ exist in both pages(?)

An interrupt will always send the PC to 0004, location 4 in the first
page.  But if your ISR is written like this (which it doesn't have to
be):

       org     4
       goto    isr

of course the goto will go to whichever page PCLATH dictates.

If you put the ISR "inline" starting at location 4 then it will execute
there regardless of PCLATH, but PCLATH would have to be saved and
modified before using any CALL or GOTO in the ISR, unless duplicate
copies of the target code are in all pages.

>I'm basing these musings on a 16C74 - but it should apply for any
>processor.

Any 14-bit (PIC 16CXX) one.  The GOTO and CALL instructions supply 11
bits of address which can cover a 2K space.  Additional bits, if required
by having more than 2K of code EPROM, are supplied from PCLATH.

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