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PICList Thread
'Power on reset'
1995\08\24@173520 by David G. Schmidt

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I have a few questions concerning power on reset of a PIC (specifically
the PIC16c54/56).  My chip is RC osc configured to run really slow
(probably 5hz)

If I have the watchdog timer set, is it active if the chip doesn't power
up reset properly?

Right now I do not have the watchdog timer set up, but
when the power droops and then comes back up, the PIC is hung.  Will a
WDT help in this case?  Would an off chip power on reset circuitry
prevent this?  I am not looking to maintain the current program, I just
want to reliably reset the PIC.

 I don't have oscilloscope measurements yet to see how low the line
droops.  The droop is just caused by myself trying to torture test my
final circuit (remove power and reapply before the filter cap
discharges).

Is part of the reason for this my very slow clock speed?

Dave
Applied Magnetics

1995\08\24@190908 by Mike Keitz

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>I have a few questions concerning power on reset of a PIC (specifically
>the PIC16c54/56).  My chip is RC osc configured to run really slow
>(probably 5hz)
>
>If I have the watchdog timer set, is it active if the chip doesn't power
>up reset properly?
>
>Right now I do not have the watchdog timer set up, but
>when the power droops and then comes back up, the PIC is hung.  Will a
>WDT help in this case?  Would an off chip power on reset circuitry
>prevent this?  I am not looking to maintain the current program, I just
>want to reliably reset the PIC.
>
>  I don't have oscilloscope measurements yet to see how low the line
>droops.  The droop is just caused by myself trying to torture test my
>final circuit (remove power and reapply before the filter cap
>discharges).


The built in power-on reset circuit is not guaranteed to work unless Vdd
starts at 0V and rises at least 0.05 V/ms.  So it will not always reset
after a "brownout".  Using the WDT should help, it's always a good idea in
any application unless extremely low power is required.  However, even with
the prescaler engaged at a rate of 128, the WDT may cause a reset every (9ms
* 128) = 1150 ms = 0.86 Hz.  Since your X1 clock is only 5 Hz, the
instruction rate is 1.25 Hz, less than twice the rate than the WDT expires.
So there'd be no way to execute enough CLRWDT instructions to stave off a
reset if the WDT in your chip was the worst case of 9 ms.  (well you could,
but every instruction in the program would have to be CLRWDT, not any time
to do anything else.)

Best bet would be to use an external voltage detector such as the MN13811
ones sold by Digi-Key to pull the reset pin low when the voltage drops.  The
Microchip data book shows a few voltage detectors that can be built with
discrete components but an integrated one is probably < $0.50 in quantity
and requires only one TO-92 unit and a pull-up resistor.

-Mike

1995\08\26@051033 by Bill Cornutt

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----------
>>I have a few questions concerning power on reset of a PIC (specifically
>>the PIC16c54/56).  My chip is RC osc configured to run really slow
>>(probably 5hz)
>>
>>If I have the watchdog timer set, is it active if the chip doesn't power
>>up reset properly?
>>

================  reply  ---------

I found that on a 16C71, the 'external power on reset circuit'
16C5X fig 13.1.1 was needed to keep it from hanging up.

  ---------
  Bill Cornutt
  spam_OUTbillcornTakeThisOuTspaminfoserv.com
  Located in Ione California USA.
  A small town in Northern California.
  Sitting against the foothills of the Mother Lode.
  ----------------------------------------------------

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