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'PIC-based Logic Analyzer. Trigger Comparator'
1998\03\02@212351 by Tom Handley

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  Several of us have discussed a PIC-based logic analyzer and/or Digital
Storage Scope. I'm hoping we can share our work and make this a group
effort. At my end, I've been busy working on low-level hardware functions.
If you are working on such a project, and if it's not a commercial product,
you might want to hold-off for awhile as I have some things to share.

  My goal is a 40Mhz logic analyzer that supports a DSO with a 20Mhz
bandwidth and standard input impedance so that you can use normal scope
probes. While I got `side-tracked' for awhile doing SPICE simulations on a
variety of analog front-ends, I finally got back to the basics of the logic
analyzer. I intend to provide the basic `hardware blocks'. Then I want to
finalize the design specification and toss it up here. At that point, we
can concentrate on software. Also, I expect this design to be fairly
affordable. So far, it looks like the core hardware will be well under $100.
This does not account for PC boards, packaging, or probes.

  My first hardware block is a 24-Bit Trigger Comparator with Bit-Enable
(ie: "Don't Care" Bits). It uses an SPI-style serial interface to load the
Bit-Enables and the Trigger Comparator Word. It also provides a Serial Data
Output and an Enable Input to support expansion.

  The design is implemented in a Lattice Semiconductor ispLSI1016-80LJ CPLD
using the Lattice ISP Synario v5.0 design environment. This device contains
2000 gates, 32 I/O Pins, 4 Dedicated Inputs, 3 Dedicated Clock Inputs, and
96 Registers. The device features +5V In-System-Programming. This version
supports 80Mhz operation and comes in a 44 Pin PLCC package. It costs around
$10. The archive includes both JEDEC and Lattice Bit Stream files for use
with the free Lattice ISP Daisy Chain Download software.

  The interface is defined as follows:

     TC0 - TC23 = Trigger Comparator Word Inputs.
           SCLK = Serial Clock Input. Clocks on Rising edge.
            SDI = Serial Data Input.
             EQ = Trigger Comparator Word Output. High = True.
            SDO = Serial Data Output for Expansion.
             EN = Enable Input for Expansion. High = Enabled.
         *RESET = Active-Low Reset for the Shift Registers.

  From a software standpoint, you send 48 Bits (MSB-first). The first 24
Bits are the Bit-Enable Qualifiers. High = Enable. The next 24 Bits are the
Trigger Compare Word Qualifiers. The *RESET is really not needed in this

  I've simulated the basic concept with Electronics Workbench v5.1. I've
also simulated functional blocks under Synario using ABEL test vectors.
Finally, I did a `static' test of the full version on a bread-board. I have
not run a dynamic test at the specified 40Mhz though the worst case routing
path is specified to 80Mhz (20ns). If your are interested in this project,
you can download the archive from my web page at:

  The archive includes the following files:

     ReadMe.txt   - Documentation
     TrigComp.dld - Bit Stream file for Daisy Chain Download Software
     TrigComp.jed - JEDEC file for third-party programmers
     PLCC44T.gif  - Package Outline and Pin Descriptions

  For more information about Lattice Semiconductor's products and to
download the free ISP Daisy Chain Download software, contact:

  If anyone uses this design, I would be interested in feedback. Thanks,

  - Tom

1998\03\04@101620 by Tom Handley

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  Linear Technology has an excellent application note in their 1993 "Linear
Applications Handbook Volume II". This is AN47; "High Speed Amplifier
Techniques. A designer's Companion for Wideband Circuitry". This covers a
wealth of information including the "ABC's of Probes" contributed by
Tektronix. One application is a 100Mhz servo controlled FET input amp with
a 10M/3pf input and 100pa bias current. The example has a gain of 10. It's
based on the LT1223 and is intended for probe and ATE pin amplifier
applications as well as A/D buffers.

  After running several simulations using a variety of vendor SPICE models,
I've decided on the above FET input amp using a MAX4100, LT1097, and FET.
Depending on the load capacitance, the 1db bandwidth was 60 to 100Mhz. It's
DC response was also very good. I'm using a 1M/20pf input impedance to
support standard X10 probes. As far as the input attenuator, I'm leaning
towards a divider and precision, low R-On, analog switches. I'm looking
at several 8-10 Bit, 40-60MPS, A/Ds. This is on hold as I'm focusing on
the logic analyzer right now.

  - Tom

At 09:09 AM 3/3/98 -0500, you wrote:
{Quote hidden}

1998\03\07@115540 by Tom Handley

picon face
  I've added a schematic for a buffered parallel port cable and programming
board that allows you to program Lattice Semiconductor's ispLSI1016,
ispLSI2032, and ispGAL22V10 devices. This is for folks that don't have
Lattice's ISP Starter Kit. It consists of a 74HC367 and a few resistors and
capacitors. You can download the archive from my web page at:

  For more information about Lattice Semiconductor's products and to
download the ISP Daisy Chain Download software and/or ISP Synario design
software, contact:

  - Tom

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