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'PIC-based Logic Analyzer - Design update'
1998\03\27@045926 by Tom Handley

picon face
 If anyone remembers, I've been working on the hardware sections of a logic
analyzer that I intend to share. My intent is to provide a versatile
hardware design so you can write you own software for a PIC or the PC
parallel port. Originally, I wanted 40Mhz, 24 channels, 128K storage, and
DSO support. I'm trying to `squeeze' most of it into 2 Lattice ispLSI1016
CPLDs. This eliminates over 25 74X family ICs and you can get the program
software for free. The programming cable can be built for $5-$10. I supply
the object files, schematic, hardware and software documentation. I have
already released the first block, a 24-Bit trigger comparator which is
programmed via a 2-wire serial interface and supports `dont-care' Bit
states.

 Lately, I've been working on the rest of the functions which include a
17-Bit SRAM address generator, 17-Bit post-trigger counter, clock divider,
and control circuitry. I've tested the individual blocks but they will not
fit in a single 1016. I can move some of it to external `glue' logic or add
another 1016. I really don't want to do this... Note, I'm using Lattice
Synario's schematic-entry and ABEL HDL design environments.

  Since this is not a commercial product, rather something to share that
will be reasonably low-cost yet provide a versatile tool, I'm having second
thoughts on how much capability is really needed. For one thing, 128K is an
`overkill'. 32K is more than sufficient for most analyzer and DSO
applications.

  While I would like to have 24 channels, 16 is still very useful. The
number of channels mainly impact the trigger word comparator which uses a
lot of the 1016's resources. The 24-Bit version uses 90%. One option I've
considered is limiting the comparator to 16 Bits and supporting up to 32
channels expandable in groups of 8.

  The post-trigger counter is another issue. It would be easier to use a
fixed, instead of programmable, counter. One possibility is to provide a
selection of fixed-length delays such as 0, 4K, 16K, and 32K samples after
the trigger. The latter is needed for DSO applications. I need to provide at
least some options for pre- and post-trigger storage.

  The following is my revised goal for this project:

1. 32K storage.
2. 16 to 32 channels. Expandable in groups of 8.
3. 16 to 24-Bit trigger word comparator.
4. 2 to 4 trigger qualifiers for signals such as *CS, *RD, *WD, *INT, etc.
5. Internal, External, and Software clocks. Clock output.
6. Internal 40Mhz clock with /10, /5, /4, /2, dividers. 40Msps to 1Ksps.
7. Selectable clock polarity.
8. 2-wire serial interface for most configuration data.

  If your are interested in this project, I would appreciate your comments.
Thanks,

  - Tom

  A schematic for a buffered parallel port cable and programming board that
allows you to program Lattice Semiconductor's ispLSI1016, ispLSI2032, and
ispGAL22V10 devices and the ispLSI1016-based 24-Bit Trigger Word Comparator
are available from my web page at:

     http://www.teleport.com/~thandley/Wilbure.htm

  For more information about Lattice Semiconductor's products and to
download the free ISP Daisy Chain Download Programming software, contact:

     http://www.latticesemi.com

1998\03\27@070248 by Alexandre Guimaraes

flavicon
face
   Have you taken a look at Atmel's 40k series ? They have some high speed
Sram inside the Fpga. It might be very useful to your project. Besides the
Sram they are giving the DOS version of the development systems for free. It
might be woth taking a look.

>   The following is my revised goal for this project:
>
>1. 32K storage.

   32K is fine for most applications. If you want it to trace program
execution 128K is better.

>2. 16 to 32 channels. Expandable in groups of 8.

   Again 16 is ok, 24 is fine for 8 bit micros and 32 is the ideal.

>3. 16 to 24-Bit trigger word comparator.

   My main problem with trigger is that it should always allow at least two
levels of trigering to be really useful, with just one comparison you are
not able to trigger on more complex events.

>4. 2 to 4 trigger qualifiers for signals such as *CS, *RD, *WD, *INT, etc.
>5. Internal, External, and Software clocks. Clock output.
>6. Internal 40Mhz clock with /10, /5, /4, /2, dividers. 40Msps to 1Ksps.
>7. Selectable clock polarity.
>8. 2-wire serial interface for most configuration data.

   Looks like a nice project. Please keep us informed on the project. If
you need help please fell free to ask for it.

>   If your are interested in this project, I would appreciate your
comments.
>Thanks,
>
>   - Tom

Best regards,
Alexandre Guimaraes
spam_OUTalexgTakeThisOuTspamiis.com.br

1998\03\28@023612 by Tom Handley

picon face
At 09:06 AM 3/27/98 -0300, Alexandre Guimaraes wrote:
>    Have you taken a look at Atmel's 40k series ? They have some high speed
>Sram inside the Fpga. It might be very useful to your project. Besides the
>Sram they are giving the DOS version of the development systems for free. It
>might be woth taking a look.

  Alexandre, I've looked at Atmel's 40K devices but they are expensive for
this project and the SRAM is limited to 18K. Also, I've used Lattice parts
for over two years and I'm use to their design environment. Lattice offers
Synario/ABEL HDL that supports their 44 pin devices for free. This is a very
powerful design environment. Most vendors offer Synario but it costs around
$1700. A fitter for all of Lattice's products costs an additional $1295...

>>3. 16 to 24-Bit trigger word comparator.
>
>    My main problem with trigger is that it should always allow at least two
>levels of trigering to be really useful, with just one comparison you are
>not able to trigger on more complex events.

  I could do a two-level trigger but that would require another CPLD and
I'm trying to avoid that. One thing that would be easy to add is a trigger
event counter to catch the nth occurance of a trigger. I'll look into it.
Thanks,

  - Tom

>Best regards,
>Alexandre Guimaraes
>.....alexgKILLspamspam@spam@iis.com.br


'PIC-based Logic Analyzer - Design update'
1998\04\04@122311 by Tom Handley
picon face
 The current state of the design supports up to 32 channels, 64K, 20-Bit
trigger comparator, and a programmable post-trigger counter. I'm still
trying to fit most of the circuitry in 2 Lattice CPLDs. The programmable
clock divider is external. You can add channels in groups of 8.

  I'd like some feedback on the post-trigger counter. Right now I have
8 programmable delays. First some background. The SRAM is configured as
a circular buffer. When a trigger event occurs, a post-trigger counter
is activated and generates a `STOP' signal at the end of the count. The
first delay is 1 cycle after the trigger. This captures everything up to the
trigger. Another delay is 65536 cycles. This captures everything after the
trigger and is required for a DSO add-on. This leaves me with 6 delays.
Right now I have them set to the folowing:

      256 Bytes
      512 Bytes
     1024 Bytes
     4096 Bytes
    16384 Bytes
    32768 Bytes

  I can easily set them to any power of 2. I'm open to suggestions.

  While the Lattice/Synario design environment has really helped with this
project, my greatest frustration is the lack of control in the placement of
logic functions given a detailed knowledge of the CPLD's `floor plan'. With
the older Lattice PDS software, I had absolute control of `what went where'.
I'm getting around 85-90% resource utilization out of the fitter. One major
advantage of Synario over PDS, is the functional waveform simulator. This
has been indispensable in this project. However it lacks timing analysis in
this version. To get the full package would cost around $3K... The older PDS
starter kit had a timing summary but no waveform simulation.

  - Tom

1998\04\05@065205 by Leon Heller

flavicon
picon face
In message <1.5.4.32.19980404172045.0066e8b8spamKILLspammail.teleport.com>, Tom
Handley <.....thandleyKILLspamspam.....TELEPORT.COM> writes
>   While the Lattice/Synario design environment has really helped with this
>project, my greatest frustration is the lack of control in the placement of
>logic functions given a detailed knowledge of the CPLD's `floor plan'. With
>the older Lattice PDS software, I had absolute control of `what went where'.
>I'm getting around 85-90% resource utilization out of the fitter. One major
>advantage of Synario over PDS, is the functional waveform simulator. This
>has been indispensable in this project. However it lacks timing analysis in
>this version. To get the full package would cost around $3K... The older PDS
>starter kit had a timing summary but no waveform simulation.

You could try the comp.arch.fpga newsgroup for this. Strictly speaking,
it's meant for the discussion of FPGA-based computer architectures, but
general FPGA and CPLD postings are acceptable.

Leon
--
Leon Heller: EraseMEleonspam_OUTspamTakeThisOuTlfheller.demon.co.uk http://www.lfheller.demon.co.uk
Amateur Radio Callsign G1HSM    Tel: +44 (0) 118 947 1424
See http://www.lfheller.demon.co.uk/dds.htm for details of my AD9850
DDS system. See " "/diy_dsp.htm for a simple DIY DSP ADSP-2104 system.

1998\04\22@065158 by Tom Handley

picon face
 The current state of the design supports up to 32 channels expandable in
groups of 8, 32K Bytes of storage, a 24-Bit trigger comparator, and a
programmable post-trigger counter. The maximum sample rate is 40Msps.
You can select 3 clock sources; external, internal clock divider, and a
host software clock. The last 2 can be used to clock the circuit under test.
You can easily add a DSO module with 8 Bits of resolution, 32K storage, and
up to 4 channels. This requires an external analog front-end with trigger
circuitry and an A/D converter.

  This version requires 3 Lattice 1016 CPLDs that include everything except
the SRAM, probe buffers (74x574s), 3-decade clock prescaler (74x390), and a
data buffer to support 4-Bit transfers. All of the configuration is handled
by a 2-wire serial interface. I designed this to support both a PIC and a PC
host with a `legacy' parallel port. It requires 17 I/O lines which consists
of 5 inputs and 12 outputs. Data is transferred to the host 4 Bits at a
time. Note, this requirement only applies to a PC host. If you use a PIC and
8 data Bits, you will need 20 I/Os. The CPLDs support both methods.

  I'm about ready to finalize the hardware design. It's time to consider
software issues. The following is the current host interface:

  SCLK  - Host Serial Configuration Clock. Active-High.
  SDI   - Host Serial Configuration Data.
          Host sends 59 Bits of data, MSB-first. This includes:
            Clock Polarity.
            Clock Source (Clock Divider, External, or Software).
            Clock Divider Prescaler (40Mhz OSC, /10, /100, /1000).
            Clock Divider /5, /4, and /2 Enables.
            Post Trigger Delay (1, 16, 64, 256, 1024, 4096, 16384, 32767).
            Trigger Bit Qualifier Enable (24 Bits).
            Trigger Bit Qualifier (24 Bits).
  CSWR  - Software Clock source.
  RCLK  - SRAM Read Clock. This line is held Low during Capture. When you
          read Address and SRAM data, the host software clocks this line.
          Data is clocked on the rising edge.
  INIT  - Initialize analyzer for Capture and, optionally, Read modes.
          Active-High.
  ARM   - Starts the Capture mode. Active-High.
  STOP  - Manually terminates the Capture mode. Overrides Automatic mode.
          Active-High.
  READ  - Sets Read mode. Active-Low.
  S0    - Read Control State select:
  S1    - "
  S2    - "
             S2 S1 S0  State
             0  0  0   SRAM Output-Enable Bank 0
             0  0  1   "                       1
             0  1  0   "                       2
             0  1  1   "                       3
             1  0  0   Current SRAM Address Bits;  0 - 3
             1  0  1   "                           4 - 7
             1  1  0   "                           8 - 11
             1  1  1   "                          12 - 14
  HLSEL - In the 4-Bit transfer mode, this selects the High or Low 4 Bits.
          This is external to the CPLDs and you would normally use a dual
          4-Bit buffer such as the 74x241 with complementary chip-selects.

  The following are host inputs:

  D0-D3 - SRAM Address/Data Bits (Optional D0-D7 for an 8-Bit Interface).
  WRITE - This is a control signal that you monitor to determine when the
          Capture mode has terminated. When this signal is Low, the Capture
          mode is active.

  One major software issue is determining where the trigger-event occurred.
The SRAM is a fixed, 32K Byte, circular buffer. After a trigger-event, a
delay counter starts. At the end of the delay count, an internal `stop'
signal is generated. The address counter holds the current address. Since
you know the size of the buffer, and you know the trigger delay, I can see a
couple of ways to determine the trigger address.

  The first method would subtract the delay from 32K and use the result to
clock RCLK to point to the current trigger address. The disadvantage is the
assumption of a 32K buffer. In this case, it really does'nt matter as the
CPLD hardware is fixed. I literally went through `fits' trying to `fit' this
design into 3 CPLDs yet I saved around two dozen 74x-family parts...

  Another method is reading the current SRAM address and subtracting the
delay to get a pointer to the trigger. This requires simple signed 15-Bit
math.

  In any case, You are working with the relative offset from the trigger
address and clocking RCLK to point to pre- and post-trigger data. An option
is provided to reset the SRAM Address to 0. In this case, in the Read mode,
you pulse INIT. The first RCLK pulse reads the absolute SRAM address 0.

  My question is; do you really need to read the trigger address in this
application (the second method)? If not, I could expand it to include
support for up to 64 channels or 56 channels with an up/down address
counter. I'd like to hear from our resident software `Gurus'. Thanks,

  - Tom

1998\04\22@072000 by Ints Mikelsons

flavicon
face
Great! And where I can get this thing?? Do you have web site?

Tom Handley wrote:

{Quote hidden}

--
With the best regards, Ints Mikelsons
(e-mail: mintsspamspam_OUTedi.lv)
(www: http://welcome.to/biocenter.lv)

1998\04\22@120330 by Tom Handley

picon face
  Ints, I have'nt put it on my web site yet as I'm still working on it. While
I've finalized the design, it's going to take awhile to generate documentation.

  What I'm doing is providing a hardware design for a logic analyzer. I would
like to see a group-effort to develop the PIC and PC software. There are a lot
of ways to package the hardware and write the software. I'm leaving that up to
members of this group. While I'll be participating in this I want to encourage
others to share in the software design. This should be educational while
providing a relative low-cost tool for development.

  - Tom

At 02:09 PM 4/22/98 +0300, Ints Mikelsons wrote:
{Quote hidden}

[snip]

1998\04\23@190929 by jimmie.funk

flavicon
face
Tom Handley wrote:
>
>    Ints, I have'nt put it on my web site yet as I'm still working on it. While
> I've finalized the design, it's going to take awhile to generate documentation
.
>
>    What I'm doing is providing a hardware design for a logic analyzer. I would
> like to see a group-effort to develop the PIC and PC software. There are a lot
> of ways to package the hardware and write the software. I'm leaving that up to
> members of this group. While I'll be participating in this I want to encourage
> others to share in the software design. This should be educational while
> providing a relative low-cost tool for development.

I'd love to help.  I've been obsessed with building low-cost test
equipment for the hobbyist/student for a while now.  I have a number of
ideas for various pieces of equipment (since I've been interested in
PICs, I've been wanting to make an integrateable design, an all-in-one
box solution that performs many functions).  Two of the most
unattainable devices, however, are scopes and analyzers, due to cost.

I have experience in C++, x86 ASM and 6811.  I also have experience in
instrumentation (all courses at school), digital/analog design and I
have just started an extracurricular effort with PICs.

What needs to be done?  What has been done?  Is there a web page for
project organization?  If not I have necessary resources and knowledge
for web-based project organization (server space, CGI, etc..).

James Oakley

@spam@cc958390KILLspamspamvulcan.northatlantic.nf.ca  -  KILLspamjimmie.funkKILLspamspamnf.sympatico.ca

1998\04\24@115650 by Tom Handley

picon face
  James, thanks for the offer. I still have some work to do before I
release it to my web page. Last night I `locked-down' the CPLD pins to
facilitate routing. That completes the CPLD core logic. I still need to
generate documentation and an overall schematic with suggested PIC and PC
parallel port connections.

  As far as software, I want this to be primarily a PIC project that
provides a serial interface between a PC host. While the PC work can be
moved to a web-based discussion, I want the PIC work to remain in this group
so others can share in it. On the PC side, the GUI can easily be designed to
support both a parallel or serial interface and that will be a separate
effort.

  The host interface is the same as I described in my recent message. I
have added 2 external triggers to better support a DSO but that does'nt
affect the software. Once I post the design on my web page we can start
getting into the software issues in detail.

  In the mean time, you may want to check my web page for a simple
programmer that allows you to program the Lattice devices. It can be built
for around free to $20 depending on what you have laying around. There's
also a link to Lattice where you will need to download the free ISP download
sotware. Note, there's also a 24-Bit trigger comparator but that's not the
version used in the logic analyzer. For more info:

     http://www.teleport.com/~thandley/Wilbure.htm

  - Tom

At 08:08 PM 4/23/98 -0230, James Oakley wrote:
>Tom Handley wrote:
[snip]

{Quote hidden}


'PIC-based Logic Analyzer - Design update'
1998\07\13@133315 by Tom Handley
picon face
 Lattice has recently released a version of Synario and their fitter that
will support their larger CPLDs. This is a six month evaluation copy. I'm
going to redesign the logic analyzer to fit into one CPLD (probably an
ispLSI1032) instead of three 1016 CPLDs. I'm not starting from `scratch' as
the redesign will mainly reduce some external wiring between the three CPLD
version.

 The current state of the design supports up to 32 channels expandable in
groups of 8, 32K Bytes of storage, a 24-Bit trigger comparator, and a
programmable post-trigger counter. The maximum sample rate is 40Msps. Sample
rates vary from 40Msps to 10sps. The post trigger delays are fixed at 1, 16,
64, 256, 1024, 4096, 16384, and 32767 Bytes. You can select 3 clock sources;
external, internal clock divider, and a host software clock. The last 2 can
be used to clock the circuit under test. There is an option to transfer 4 or
8 Bits at a time.

  The new version will require 1 Lattice CPLD that includes everything
except the SRAM, probe buffers (74ACT574s) and SRAM data buffers (74HCT244s)
to support 4 or 8-Bit transfers. All of the configuration is handled by a
2-wire serial interface. I designed this to support both a PIC and a PC host
with a `legacy' parallel port. In the 4-Bit transfer mode it requires 15 I/O
lines and 19 in the 8-Bit mode.

  I'm going to look into increasing the trigger comparator to 32 Bits and
increasing the memory size from 32K Bytes. Multiple trigger levels was
suggested earlier but that would require several CPLDs as I would need to
duplicate the trigger comparator for each level. The comparator uses a lot
of pin and macrocell resources. This is not a simple equality comparator. It
provides for individual Bit don't-care states and it's configured by buried
shift registers.

  You can easily add a DSO module with 8 Bits of resolution, 32K storage,
and up to 4 channels. This requires an external analog front-end with
trigger circuitry and an A/D converter. I've run several SPICE simulations
on a DSO front-end mainly based on Linear Technology, Maxim, and Analog
Devices op-amps. In all versions, there will be at least a 50Mhz +/- 1db
bandwidth for a sampling rate of 40 Msps. The DC performance should compare
with existing commercial products. The phase margins have varied quite a bit
but I consider this a low priority for this project. The input impedance and
capacitance will be compatible with standard scope probes (1Meg/20pf).
Obviously it will be up to the user to ensure proper layout/construction
techniques. However, I need to first concentrate on the basic logic analyzer
which is at the core of any DSO add-on.

  The following is the current three CPLD host interface which should be
very close to the single CPLD interface:

  SCLK  - Host Serial Configuration Clock. Active-High.
  SDI   - Host Serial Configuration Data.
          Host sends 60 Bits of data, MSB-first. This includes:
            Clock Polarity (Active Edge).
            Clock Source (Clock Divider, External, or Software).
            Clock Divider Prescaler (40Mhz OSC, /10, /100, /1000, /10000,
                                                /100000).
            Clock Divider /5, /4, and /2 Enables.
            Post Trigger Delay (1, 16, 64, 256, 1024, 4096, 16384, 32767).
            Trigger Bit Qualifier Enable (24 Bits).
            Trigger Bit Qualifier (24 Bits).
  FSWR  - Software Clock source.
  RCLK  - SRAM Read Clock. This line is held Low during Capture. When you
          read SRAM data, host software clocks this line on the rising edge.
  INIT  - Initialize analyzer for each sample capture. Active-High.
  ARM   - Starts the Capture mode. Active-High.
  STOP  - Manually terminates the Capture mode. Overrides Automatic mode.
          Active-High.
  READ  - Sets Read mode. Active-Low.
  S0    - Read Control State select:
  S1    - "
  S2    - "
          This provides the SRAM 74HCT244 data buffer chip selects.
          There are 8 in the 4-Bit mode and 4 in the 8-Bit mode.
  WRITE - This is a control signal that you monitor to determine when the
          Capture mode has terminated. When this signal is Low, the Capture
          mode is active. The host software determines the relative
          trigger address given a 32K circular buffer and the known
          post-trigger delay.

  MODE  - This line is tied Low for 4-Bit transfers and High for 8-Bits.

  - Tom

1998\07\14@054950 by Pavel Korensky

flavicon
face
At 10:31 13.7.1998 -0700, you wrote:
>  The current state of the design supports up to 32 channels expandable in
>groups of 8, 32K Bytes of storage, a 24-Bit trigger comparator, and a
>programmable post-trigger counter. The maximum sample rate is 40Msps. Sample
>rates vary from 40Msps to 10sps. The post trigger delays are fixed at 1, 16,
>64, 256, 1024, 4096, 16384, and 32767 Bytes. You can select 3 clock sources;
>external, internal clock divider, and a host software clock. The last 2 can
>be used to clock the circuit under test. There is an option to transfer 4 or
>8 Bits at a time.
>

Nice design, but one small comment. Why is not possible to go higher in
sample frequency ? I think that it should be possible with fast cache RAM
and isp1032 in 125 Mhz version. Maybe up to 100 Mhz.

>   The new version will require 1 Lattice CPLD that includes everything
>except the SRAM, probe buffers (74ACT574s) and SRAM data buffers (74HCT244s)
>to support 4 or 8-Bit transfers. All of the configuration is handled by a
>2-wire serial interface. I designed this to support both a PIC and a PC host
>with a `legacy' parallel port. In the 4-Bit transfer mode it requires 15 I/O
>lines and 19 in the 8-Bit mode.

Perfect.

>
>   I'm going to look into increasing the trigger comparator to 32 Bits and
>increasing the memory size from 32K Bytes. Multiple trigger levels was
>suggested earlier but that would require several CPLDs as I would need to
>duplicate the trigger comparator for each level. The comparator uses a lot
>of pin and macrocell resources. This is not a simple equality comparator. It
>provides for individual Bit don't-care states and it's configured by buried

>shift registers.

And what about a somehow "modular" design. One level of trigger comparators
can be in main ispLSI1032 and the further stages can be in optional pairs
of 1016. With empty PLCC sockets on PCB, user can add further stages (let's
say up to four). With some glue logic in main 1032, several kinds of
"trigger magic" can be possible, like ORing, ANDing etc. Also one can
program sequential trigger with this design.

{Quote hidden}

Also very interesting.

Very good work

PavelK

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1998\07\15@104200 by Tom Handley

picon face
  Pavel, first I need to retract my earlier statement about fitting this in
one ispLSI1032. I will need at least one additional 1016 or a 1048 but that
requires a PQFP package which defeats one goal of this design; cheap and
easy to construct... I did a quick check of Hamilton/Hallmark's web site and
the original ispLSI1016-90s I specified are still $9.75 in unit quantities.
/E versions cost less and they are pushing folks towards that version. In
the case of the 1032Es, there is a major difference in price and they are
in-stock. They quote $13.75 for the 70Mhz version and $28.75 for 100Mhz. I
also noticed that the lead-times for non-/E parts range from 56 to 70
days... I'll call my local rep and get /E samples of the 1016 and 1032.

re: Sample rate limit of 40Msps and purpose of this project

  I used that limit as it seems more practical for the majority of folks.
You can easily scale this to 100Msps using selected components and proper
construction techniques. Again, the purpose of this project (which I'm doing
in my spare time) is to provide an affordable logic analyzer with reasonable
capabilities, that most folks can easily construct. I also wanted to provide
an opportunity to our novice users to see and/or participate in the software
design process guided by our resident experts. I'm just the hardware guy ;-)
I've been in this list around three years and I've learned so much from
the `wealth' of expertise in a variety of fields, that I wanted to give
something back. Also, our novice members probably don't realize that when
they ask `seemingly dumb' questions, many of us who have been in the field a
long time, `dig-out' books and look into subjects that many of us have not
visited in a long time. This whole process feeds on itself and we all learn,
from novice to experts. I'm willing to bet that the majority of replies in
this list come from folks that take some time doing a little background
research to the question at hand. This spirit of sharing and helping is what
makes this list the great resource it is.

re: Trigger comparators and modular design

  Good point and it's perfect for the current design! One of the 1016s
provide the 24-Bit comparator function. I'm getting a pin and macrocell
utilization rate in the high 90s. Of the three chips, that makes best use of
the chip's resources. I designed it to be expandable but I did not utilize
that capability in the 3-chip version. This frees-up the 1032 to provide the
control circuitry, clock dividers, host interface, chip-selects, address
generator, post-trigger delays, and trigger logic.

  - Tom

At 11:38 AM 7/14/98 +0200, Pavel Korensky wrote:
{Quote hidden}


'PIC-based Logic Analyzer - Design update'
1998\08\06@100035 by Tom Handley
picon face
  First, for those of you who have not been following this, please check
the PIC List archives for the above subject line.

  After upgrading to the Lattice/Synario v5.1 environment, my first
priority was converting the earlier 3-chip design based on the Lattice
ispLSI1016 to a 2-chip design based on the ispLSI1032E and 1016E. While, as
of 4 Aug 98, this will add $16 to the cost, I've increased the trigger
comparator to 32 Bits and provided a simple programmable external triggering
facility. It also provides for a small reduction in board `real-estate'. The
main changes from the earlier specification are:

  The trigger Comparator is now 32 Bits. Instead of sending 24 Bits for the
trigger enable and then 24 Bits for the trigger qualifier, you now send 8
Bits for enable, and 8 Bits for the qualifier. This is repeated for each
bank of 8 channels. 64 Bits total. If you only implement one bank, you still
need to send 64 Bits as this serial data `ripples through' to the other
configuration data.

  I've added two external triggers. One is active-High and the other is
active-Low. These are combined with the above trigger comparator and fed
into an _AND_ gate. You can enable/disable each one during the serial
configuration process. This allows for such combinations as:

     Trigger Comparator   or...
     TRIGA   (This is good for a DSO add-on)   or...
     Trigger Comparator _AND_ TRIGA _AND_ !TRIGB

  Now I realize it would be nice to add a lot more options here but I've
run out of resources on the 1032E. While the chip provides 6000 gates, I
could'nt add another function even if I had a sub-micron `crowbar'... This
is actually a credit to the fitter. I'm real pleased with the utilization of
the 1032E and the 1016E's resources. Note, the 1016E contains the SRAM
address generator and the clock prescalers/dividers.

  The internal sampling rates now range from 40Msps to 100sps. This
includes a programmable 4-decade prescaler followed by individually enabled
/5/4/2 dividers. More on practical sampling rates follows but first a brief
summary on how the analyzer works. Once `armed', the analyzer captures data
in a 32K circular buffer until a trigger-event. Then it continues to capture
a fixed number of samples determined by a programmable post-trigger counter.

  While I've ran across some `quirks' in the Lattice/PDSPlus timing
analyzer, it has proved very valuable in providing detailed propagation
delays from one node to another. The first revelation is that, when using
the trigger comparator, it will not support a 40Msps sample rate. 20Msps is
much more reasonable. Once triggered, it should sustain a 35-40Msps sample
rate but it could miss the first sample after the trigger when using the
higher sample rates. The basic comparator has a 20.7ns delay and I've run a
variety of logic reduction techniques in Synario, Electronics Workbench v5,
and manually. Add to this a 6-8ns delay with a 74F or 74ACT574 pod buffer,
SRAM address counter delay, and the SRAM setup time. I've been testing this
with a 100Mhz part. You can also get a 125Mhz part but you only save 3-4ns
and the cost ($28 vs. $42) is not worth it. I've looked at several other
logic analyzer projects in Electronics Now and Circuit Cellar Ink (Including
this month's article) and they have the same problem with the trigger to
capture delay. Normally this won't be an issue. Also, when using the
external triggers for DSO applications, you should be able to sustain
40Msps. For my design, I'm specifying a 74ACT574 pod buffer, 100Mhz
1032E/1016E, and 12ns SRAMs. For a `reality check', most all current
microcontrollers run with a bus speed of 5Mhz or less.

  I still need to do some static tests on a breadboard. I also want to look
at the possibilities of using two 1032Es to add more capability. The current
design, using the 1032E/1016E, is `locked down' but as I explore the options
with two 1032Es, I'm sure I'll be asking for suggestions from this group.
I also need to update my ispLSI programmer schematic to cover the 1032E
which is an 84-pin PLCC device. I should have that on my web page within a
week and I'll post an update here.

  - Tom
Tom Handley
New Age Communications
Since '75 before "New Age" and no one around here is waiting for UFOs...

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