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PICList Thread
'Indirection on 16C84'
1998\04\16@052121 by AutismUK

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I have a query. I can't find an answer in the FAQ. I would be
grateful if an expert could clarify this.

In the FSR register on a 16C84 is it 8 bit or 7 bit ? I am
confused by the 16C84 Data sheet Microchip have which
can't seem to make its mind up :-

In Section 4.5 (FSR & INDF) of the datasheet it says "an effective 9
bit address is gained by concatenating FSR and IRP"

In Section 4.2 (Data memory organisation) it says "Indirect
addressing uses the present value of RP1:RP0 for access
into the banked areas of data memory" (4th paragraph)

In Table 4-1 (Reg summary) it shows FSR to be an 8 bit register,
implying all bits used.

On the block diagram 3-1 it shows FSR->AdrMux with Instruction
Reg to be a 7 bit wide path.

If I put $81 in FSR and use INDF do I get always get
OPTION or does it depend on RP0 - will I get TMR0 sometimes ?

Thanks, Paul Robson (spam_OUTautismukTakeThisOuTspamaol.com)

1998\04\16@113224 by Mike Keitz

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On Thu, 16 Apr 1998 05:10:41 EDT AutismUK <.....AutismUKKILLspamspam@spam@AOL.COM> writes:
>I have a query. I can't find an answer in the FAQ. I would be
>grateful if an expert could clarify this.
>
>In the FSR register on a 16C84 is it 8 bit or 7 bit ? I am
>confused by the 16C84 Data sheet Microchip have which
>can't seem to make its mind up :-
>

It's 8 bits.  For example, setting FSR to 0x81 will make INDF access the
OPTION register, not TMR0, regardless of the RP0 bit.  Since the 84 has
only two register pages, the RP1 and IRP bits are not necessary.  The
value in them is ignored entirely.

>In Section 4.5 (FSR & INDF) of the datasheet it says "an effective 9
>bit address is gained by concatenating FSR and IRP"

This is true, but only of academic interest since IRP is not used on the
16X84.

>In Section 4.2 (Data memory organisation) it says "Indirect
>addressing uses the present value of RP1:RP0 for access
>into the banked areas of data memory" (4th paragraph)

This is wrong.  Don't believe everything you read.  Interestingly the
error persists onto the 16F84 data sheet on the '97 CD.

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1998\04\16@114539 by Marc Heuler

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Hi AutismUK (AutismUK), in <2395e7b5.3535cb12spamKILLspamaol.com> on Apr 16 you wrote:

> If I put $81 in FSR and use INDF do I get always get
> OPTION or does it depend on RP0 - will I get TMR0 sometimes ?

FSR can access the second bank, so you always get OPTION.  I use this often
when I need PORTB and TRISB accesses very quickly.  I then use PORTB
directly, and TRISB (just as quick) via FSR.

The manual probably meant that the _9_ bit address is built from RP1 and 8
bit FSR.

1998\04\16@191846 by TONY NIXON 54964

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The IRP bit is not used on the 16C(F)84 chips. It would be used if
the RAM map exceeded 256 locations, hence the need for 9 bits.

RP1 and RP0 are used for DIRECT addressing, not INDIRECT addressing.
These bits are needed because the instructions which specify a RAM address
are only 7 bits long.  Thus to make an 8 bit address to access the
256 bytes of RAM you have to use RP0. RP1 is not used on the
16(F)C84 chips.

The FSR is an 8 bit register.

The address MUX can only use 7 bits of the RAM address data from the
FSR. Bit 7 of the FSR is used to set the Ram Page. Bit 7 = 0, RAM Page 0, Bit 7
= 1, RAM Page 1. Thus the FSR by itself can indirectly address all of the 256
RAM locations. The IRP bit is not used on the 16(F)C84, because there
are only 8 bits needed to access the RAM.

$81 in the FSR will always indirectly address the OPTION register.
$01 in the FSR will always indirectly address the TMR0(RTCC) register.
RP0 has no effect on INDIRECT addressing.

If this still confuses you, check out the web site below.


Regards

Tony


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1998\04\16@215024 by paulb

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AutismUK wrote:

> In the FSR register on a 16C84 is it 8 bit or 7 bit ?

 It's unquestionably 8-bit.  You can use it to do maths with.

> I am confused by the 16C84 Data sheet Microchip have which can't seem
> to make its mind up :-

 Common enough problem.  The datasheets tend to describe a chip which
they *might* make as well as the one they do.  You have to .and. the
information given!

> In Section 4.5 (FSR & INDF) of the datasheet it says "an effective 9
> bit address is gained by concatenating FSR and IRP"

 Can't *find* any section 4.5 in my .pdf file!  Section 4.4 ends on
page 18 and section 5.0 starts on page 19.  Nevertheless, figure 4.7,
still on page 18 explains that registers are either addressed directly
using 7 bits of the opcode and RP0;RP1, totalling 9 bits, or indirectly
using 8 bits of FSR plus IRP (note; *not* RP0 or RP1), again totalling
9 bits.  Since however there is no bank 2 or 3 in the '84, RP1 and IRP
are not used and should be set to zero for guaranteed operation.

> In Section 4.2 (Data memory organisation) it says "Indirect
> addressing uses the present value of RP1:RP0 for access
> into the banked areas of data memory" (4th paragraph)

 It does say that.  It's garbage!  Poor proof reading.

> In Table 4-1 (Reg summary) it shows FSR to be an 8 bit register,
> implying all bits used.

 Yep!

> On the block diagram 3-1 it shows FSR->AdrMux with Instruction
> Reg to be a 7 bit wide path.

 It should say "7 or 8", shouldn't it?  But if you're that picky, there
should be "2 or 3" bits of the Status register (i.e., RP0, RP1, IRP)
going to the Adr Mux also and these aren't shown at all.  Fair go, it's
just a "there are thingies in the chip" type of diagram!

 What one does wonder, is whether the parts of the 9th bit path
actually exist within the chip ready for the later version and are
unused, or whether they've been optimised out by the silicon compiler?

> If I put $81 in FSR and use INDF do I get always get OPTION

 Yep.

> or does it depend on RP0 - will I get TMR0 sometimes?

 Nope.

 Cheers,
       Paul B.
(No warranty, express or implied!)

1998\04\17@025423 by Caisson

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> Van: AutismUK <.....AutismUKKILLspamspam.....AOL.COM>
> Aan: EraseMEPICLISTspam_OUTspamTakeThisOuTMITVMA.MIT.EDU
> Onderwerp: Indirection on 16C84
> Datum: donderdag 16 april 1998 11:10
>
> I have a query. I can't find an answer in the FAQ. I would be
> grateful if an expert could clarify this.
>
> In the FSR register on a 16C84 is it 8 bit or 7 bit ? I am
> confused by the 16C84 Data sheet Microchip have which
> can't seem to make its mind up :-

It is a 8-Bit register. Try it out by writing a 0x00. Now read it.
Do the same with 0x80.

> In Section 4.5 (FSR & INDF) of the datasheet it says "an effective 9
> bit address is gained by concatenating FSR and IRP"

When using an _indirect_ adres (read/write INDF) you have got a
9-bit adress space.  they are mostly represented as 4 blocks of 128
registers.  This is because most instructions regarding registers have
only 7 bits to adress a register (the 8-th bit is used to tell it where to
put the result : Register or W)

So, Indirect adressing uses the IRP (Indirect Register Page) -bit as
a 9-th bit.

Oh, By the way :  The last line in example 4-2 : 'How to clear RAM
using indirect addressing' states : Forget the IRP-bit : you've got only
2 pages of RAM (2* 128 := 256 -> adressable by the FSR register alone)

> In Section 4.2 (Data memory organisation) it says "Indirect
> addressing uses the present value of RP1:RP0 for access
> into the banked areas of data memory" (4th paragraph)

Uh Oh ...  A Typo !  It _should_ read : 'Direct adressing uses' etc.

> In Table 4-1 (Reg summary) it shows FSR to be an 8 bit register,
> implying all bits used.

That's correct.

> On the block diagram 3-1 it shows FSR->AdrMux with Instruction
> Reg to be a 7 bit wide path.

RAM file registers 36 * 8  ?  What the [Censored] does that mean ?
A register is 8 bits wide, but we 've got 2*32 registers !

Did you see that the 'Direct Addr' path seems to be only 5 bits wide ?
That should be 7 bits ...

Typo, Typo ...

And where are the Bank-select bits added ?

> If I put $81 in FSR and use INDF do I get always get
> OPTION or does it depend on RP0 - will I get TMR0 sometimes ?

Look at figure 4-2, the Register file map.  Register 0x81 _is_ the OPTION
-register.  And No, you won't get TMR0. Never.
Unless ... You load FSR with 0x01 :-)

> Thanks, Paul Robson (autismukspamspam_OUTaol.com)

You're welcome.  Really. No, I mean it !
(  Jeess ... Wat a slow day makes you say .. ;-)

Greetz,
 Rudy Wieser

P.S.
Did you see that the RP1 bit is ignored too ? like the IRP-bit and for
the same reason.  Only 2*32 registers.

1998\04\17@051823 by AutismUK

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In a message dated 16/04/98 23:19:09 GMT, you write:

> The IRP bit is not used on the 16C(F)84 chips. It would be used if
[snip]
>
>  If this still confuses you, check out the web site below.

Thanks to everyone who replied...

I do understand the idea and thought the 8 bit FSR was
the most likely answer, just wanted to check & didn't have a
real one to work one (yet). (I'll be a bit more cynical about the
datasheets too)

Paul Robson (@spam@autismukKILLspamspamaol.com)

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