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'ESD discussion, WAS: Un-erasable memory in a 16C74'
1998\03\12@185330 by Morgan Olsson

picon face
At 11:51 1998-03-12 -0800, you wrote:
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properhandeling.
>( Kind of difficult to short Vcc and Vdd every time when you
>program the chip and run to the unit to place in and make sure it is working
>especially if your boss is behind you and kindly remind you this project was
>due two weeks ago.)

I think that is a Boss«s natural behaviur,
as they don«t alwaus understand the nature of development.
Just accept it  :)

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The factors we are talking about here are factors not critical at normal use.
Example: The design will work properly either it is the transistor Q2356 or
Q2341 that will brake down at 20V Vdd.

>The latest silicon processig technology is so good they manufacturing
millions of
>pieces with a very low fallout and if you measured them they are pretty
well the
>same.
>But I was talking about the layout inside of the chip, on the silicon. As
you know
>they have  wires,
>jumpers, gates .... processed from silicon. My understanding is, this
layout has
>weeknesses
>as a usual layout has. If they have to wire to close or sharp corners...
the ESD
>going to
>strike there, because looking for the easiest path to discharge.

Don«t the silicon design programs have same style or better design rule
checking as PCB-cad?!

Well, it«s hard to calculate impedance effects, and probably they design
aiming more for best normal function than astronomous EDS protection...

>I had MOS-Fet transistor ESD damage picture taken with electron microscope
>and clearly shows ESD was strike where the gate insulation was the weakest.

Interesting.

If the process is at theoretically optimum the the gate insulations
everywhere would be about the same.  Due to extremely little mechanical and
optical misalignment, thermal variation, chemistry etching flow variation
etc, the chips in a wafer will not be exactly the same, as not the
differences between parts of same chip, although they might all work to the
spec.  

The margins for a digital chip to work and differ ones from zeroes is huge,
compared to deviation in linear bahaviour and ESD capacity.

/Morgan

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Pic's
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remedied
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/  Morgan Olsson, MORGANS REGLERTEKNIK, SE-277 35 KIVIK, Sweden \
\  .....mrtKILLspamspam.....iname.com, ph: +46 (0)414 70741; fax +46 (0)414 70331    /

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