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'[ee] interesting micro-FPGA devices - 10F alternat'
2011\10\14@105509 by Mike Harrison

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www.silego.com/
Greenpak devices
Micro FPGA with analogue functions, cheap ($0.24 100x), 1.8-5V supply (GreenPak2 version), schematic
based devtool, and unlike all other current FPGAs, internals are fully documented.
Only downside I can see is that it's OTP, presumably to save cost.

2011\10\14@114536 by V G

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On Fri, Oct 14, 2011 at 10:55 AM, Mike Harrison <spam_OUTmikeTakeThisOuTspamwhitewing.co.uk>wrote:

> http://www.silego.com/
> Greenpak devices
> Micro FPGA with analogue functions, cheap ($0.24 100x), 1.8-5V supply
> (GreenPak2 version), schematic
> based devtool, and unlike all other current FPGAs, internals are fully
> documented.
> Only downside I can see is that it's OTP, presumably to save cost.
>
>
One time programmable is a dealbreaker :

2011\10\14@120432 by Herbert Graf

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On Fri, 2011-10-14 at 15:55 +0100, Mike Harrison wrote:
> http://www.silego.com/
> Greenpak devices
> Micro FPGA with analogue functions, cheap ($0.24 100x), 1.8-5V supply (GreenPak2 version), schematic
> based devtool, and unlike all other current FPGAs, internals are fully documented.
> Only downside I can see is that it's OTP, presumably to save cost.

OTP does not an FPGA make. The whole point of FPGAs are their field
programmability.

I can't imagine trying to debug a design on a OTP device. It looks like
they don't have any option to test your design other then simulating
(which is NEVER enough) or going through tons of OTP parts to figure out
what's wrong.

Neat, but frankly I'll pass until there is another devel option
available.

TTYL

2011\10\14@122740 by Mike Harrison

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On Fri, 14 Oct 2011 12:04:29 -0400, you wrote:

>On Fri, 2011-10-14 at 15:55 +0100, Mike Harrison wrote:
>> http://www.silego.com/
>> Greenpak devices
>> Micro FPGA with analogue functions, cheap ($0.24 100x), 1.8-5V supply (GreenPak2 version), schematic
>> based devtool, and unlike all other current FPGAs, internals are fully documented.
>> Only downside I can see is that it's OTP, presumably to save cost.
>
>OTP does not an FPGA make. The whole point of FPGAs are their field
>programmability.

It isn't aimed at reprogrammable applications. How often do you reprogram a 10F after a product has shipped?

>I can't imagine trying to debug a design on a OTP device. It looks like
>they don't have any option to test your design other then simulating
>(which is NEVER enough) or going through tons of OTP parts to figure out
>what's wrong.

Obviously they are not aiming this at people who are prepared to pay for reprogrammability,

2011\10\14@123954 by Dave Tweed

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Herbert Graf wrote:
> On Fri, 2011-10-14 at 15:55 +0100, Mike Harrison wrote:
> > http://www.silego.com/
> > Greenpak devices
> > Micro FPGA with analogue functions, cheap ($0.24 100x), 1.8-5V supply
> > (GreenPak2 version), schematic based devtool, and unlike all other current
> > FPGAs, internals are fully documented.
> > Only downside I can see is that it's OTP, presumably to save cost.
>
> OTP does not an FPGA make. The whole point of FPGAs are their field
> programmability.

The alternative to field programmable is factory (i.e., mask) programmable,
which requires large NRE charges and large minimum quantities. Any form of
field programmability, including OTP, is a huge advantage for certain types
of development.

> I can't imagine trying to debug a design on a OTP device. It looks like
> they don't have any option to test your design other then simulating
> (which is NEVER enough) or going through tons of OTP parts to figure out
> what's wrong.

Are you an engineer or a hacker? I developed my FPGA chops over many years
on Actel's lines of OTP (antifuse-based) FPGAs, with designs in the range of
thousands of gate-equivalents. With proper design discipline in the first
place, and the willingness to wring as much information as possible out of
each design iteration, OTP was never a real problem.

-- Dave Twee

2011\10\14@125121 by Herbert Graf

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On Fri, 2011-10-14 at 17:27 +0100, Mike Harrison wrote:
> On Fri, 14 Oct 2011 12:04:29 -0400, you wrote:
>
> >On Fri, 2011-10-14 at 15:55 +0100, Mike Harrison wrote:
> >> http://www.silego.com/
> >> Greenpak devices
> >> Micro FPGA with analogue functions, cheap ($0.24 100x), 1.8-5V supply (GreenPak2 version), schematic
> >> based devtool, and unlike all other current FPGAs, internals are fully documented.
> >> Only downside I can see is that it's OTP, presumably to save cost.
> >
> >OTP does not an FPGA make. The whole point of FPGAs are their field
> >programmability.
>
> It isn't aimed at reprogrammable applications.
> How often do you reprogram a 10F after a product has shipped?

True, but how many times do you reprogram a 10F while DEVELOPING your
product?

I have no problem with the idea of OTP PL, the issue is there is zero
devel options other then sim, as far as their website indicates to me.

TTYL

2011\10\14@130722 by V G

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On Fri, Oct 14, 2011 at 12:39 PM, Dave Tweed <.....picKILLspamspam@spam@dtweed.com> wrote:

>  Are you an engineer or a hacker?
>

Irrelevant. There don't seem to be any development options available. As has
been stated before, simulation only is most likely not enough. Testing needs
to take place, and reprogrammable during testing is a must - unless you have
endless funding available to dispose used parts

2011\10\14@132628 by M.L.

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On Fri, Oct 14, 2011 at 12:57 PM, V G <x.solarwind.xspamKILLspamgmail.com> wrote:
> Irrelevant. There don't seem to be any development options available. As has
> been stated before, simulation only is most likely not enough. Testing needs
> to take place, and reprogrammable during testing is a must - unless you have
> endless funding available to dispose used parts.

If "endless funding" is $100, then yes. You would need "endless
funding" for $0.25 chips.

-- Martin K

2011\10\14@132708 by Harold Hallikainen

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Remember the PIC18C parts that were available in ceramic (erasable) or
plastic (OTP) packages? I wonder if a UV erasable part is available.
Unless the part uses fuse blowing for programming, it seems that
everything now would use reprogrammable flash. But, I don't design the
chips! I really like the current on chip debugging capabilities (I use
REAL-ICE). I started with a Microchip emulator where it was maybe $1,000
for the box and anther $800 for each processor to be supported.

Harold

Harold


{Quote hidden}

>

2011\10\14@133811 by Mike Harrison

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On Fri, 14 Oct 2011 12:51:18 -0400, you wrote:

>On Fri, 2011-10-14 at 17:27 +0100, Mike Harrison wrote:
>> On Fri, 14 Oct 2011 12:04:29 -0400, you wrote:
>>
>> >On Fri, 2011-10-14 at 15:55 +0100, Mike Harrison wrote:
>> >> http://www.silego.com/
>> >> Greenpak devices
>> >> Micro FPGA with analogue functions, cheap ($0.24 100x), 1.8-5V supply (GreenPak2 version), schematic
>> >> based devtool, and unlike all other current FPGAs, internals are fully documented.
>> >> Only downside I can see is that it's OTP, presumably to save cost.
>> >
>> >OTP does not an FPGA make. The whole point of FPGAs are their field
>> >programmability.
>>
>> It isn't aimed at reprogrammable applications.
>> How often do you reprogram a 10F after a product has shipped?
>
>True, but how many times do you reprogram a 10F while DEVELOPING your
>product?

With devices this simple, probaly not that many, and if the product volume is such that the low part
cost is an advantage, extra dev costs of socketing etc. on a proto are negligible. ~$20 buys you about a hundred re-spins.

2011\10\14@133945 by Dwayne Reid

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At 10:57 AM 10/14/2011, V G wrote:

>Irrelevant. There don't seem to be any development options available. As has
>been stated before, simulation only is most likely not enough. Testing needs
>to take place, and reprogrammable during testing is a must - unless you have
>endless funding available to dispose used parts.

When Microchip first introduced the 12c508 (the first 8-pin PIC ever produced), the only package option was OTP.  Microchip promised us to supply us as many chips as we needed (for free) to debug our products.

Even with unlimited quantities of chips available for free, my most complex design took no more than 7 or 8 iterations.  At a buck a chip, this was reasonable and I don't think that we ever bothered our disti for the freebies.

Some time later, Microchip was able to source a ceramic package with quartz window to allow erasing and re-programming.

The point that I'm making is that if these parts are the simple, low end parts that they seem to be, spending a few bucks prototyping the design seems entirely reasonable to me.

dwayne

-- Dwayne Reid   <EraseMEdwaynerspam_OUTspamTakeThisOuTplanet.eon.net>
Trinity Electronics Systems Ltd    Edmonton, AB, CANADA
(780) 489-3199 voice          (780) 487-6397 fax
http://www.trinity-electronics.com
Custom Electronics Design and Manufacturing

2011\10\14@134046 by Mike Harrison

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On Fri, 14 Oct 2011 12:57:42 -0400, you wrote:

>On Fri, Oct 14, 2011 at 12:39 PM, Dave Tweed <picspamspam_OUTdtweed.com> wrote:
>
>>  Are you an engineer or a hacker?
>>
>
>Irrelevant. There don't seem to be any development options available. As has
>been stated before, simulation only is most likely not enough. Testing needs
>to take place, and reprogrammable during testing is a must - unless you have
>endless funding available to dispose used parts.

At ~$20 per hundred, cost of parts eaten in development is negligible compared to other costs.
Remember these are very simple parts, and assuming the devtools are good, lilkely to be less cope
for the sort of coding errors you get when writing MCU code. Of course it would be nice to have reprogrammable parts, but they are clearly aiming at minimum
cost- maybe as & when they decide to move to lower volume customers- I read that they've already
shipped 100 million parts.

2011\10\14@134957 by V G

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On Fri, Oct 14, 2011 at 1:25 PM, M.L. <@spam@mKILLspamspamlkeng.net> wrote:

>  If "endless funding" is $100, then yes. You would need "endless
> funding" for $0.25 chips


As many here would like to believe, time = money. Not only do you have to
waste money by purchasing new chips, you would also have to
desolder/resolder/whatever every time you program. It's a huge hassle.
Especially for tiny, no lead parts like those

2011\10\14@135701 by Herbert Graf

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On Fri, 2011-10-14 at 12:39 -0400, Dave Tweed wrote:
> Are you an engineer or a hacker?
For FPGA work? Engineer. My hobby type work is usually with other stuff.

But I must ask: what difference does that make? Had I responded
"hobbyist" for FPGA work would my opinion have meant less to you? Why?

> I developed my FPGA chops over many years
> on Actel's lines of OTP (antifuse-based) FPGAs, with designs in the range of
> thousands of gate-equivalents. With proper design discipline in the first
> place, and the willingness to wring as much information as possible out of
> each design iteration, OTP was never a real problem.

I've done the OTP style development (man moons ago), it's something I
will never go back to.

No matter how "careful" you are, any design will require many
iterations. The thought of relying on SIM to deal with the majority of
iterations is frankly scary.

Simulation is a useful tool, but it is never a replacement for real
hardware debug. This product seems to be targeted at the mindset that
sim flushes everything out. That's a scary mindset IMHO.

TTYL

2011\10\14@140053 by Bob Ammerman

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From: "V G" <KILLspamx.solarwind.xKILLspamspamgmail.com>
> One time programmable is a dealbreaker :(

Not at 0.24 each.

Assume you spend as little as 10 minutes coming up with each version of the chip.

An hours worth of chips is then less than a buck and a half.

Your time is worth a lot more than that!

-- Bob Ammerman
RAm Systems

2011\10\14@140521 by Bob Ammerman

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I don't think it is practical to reprogram these in circuit. The whole point is the tiny footprint. It would take many times the board space for all the components that would be needed to isolate the programming functionality from the application functionality, not to mention some kind of connector for the reprogramming.

Think of these as jelly bean parts. Just program them and be done with it.

If  you read their datasheet closely you'll see that their primary model is the have them program the chips in their factory after the design is frozen.. They are obviously looking for high-quantity applications.

-- Bob Ammerman
RAm Systems

2011\10\14@141923 by Bob Ammerman

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----- Original Message ----- From: "V G" <RemoveMEx.solarwind.xTakeThisOuTspamgmail.com>
To: "Microcontroller discussion list - Public." <spamBeGonepiclistspamBeGonespammit.edu>
Sent: Friday, October 14, 2011 1:49 PM
Subject: Re: [ee] interesting micro-FPGA devices - 10F alternative?


{Quote hidden}

Yeah, the desolder/resolder time is the real killer here. You might want to develop your prototype with some sort of ZIF socket, like they have on their development platform/programmer.

-- Bob Ammerman
RAm Systems

2011\10\14@142331 by Bob Ammerman

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>I don't think it is practical to reprogram these in circuit. The whole
>point
> is the tiny footprint. It would take many times the board space for all
> the
> components that would be needed to isolate the programming functionality
> from the application functionality, not to mention some kind of connector
> for the reprogramming.

Hm... crazy idea for a product like this that would be reprogrammable....

Answer to isolation for programming and to board space for connector....

Create a special bond-out chip for development (or reprogrammability of a production chip) that has contacts on the top (for programming) as well as the bottom (soldered in for the application).

Then a probe that fits right over the top of the chip would allow you to reprogram without requiring any additional board space. Just hold the probe on the chip, hit the program button, wait a few seconds, and you're all set!

-- Bob Ammerman
RAm Systems

2011\10\14@150108 by Dave Tweed

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Herbert Graf wrote:
> On Fri, 2011-10-14 at 12:39 -0400, Dave Tweed wrote:
> > Are you an engineer or a hacker?
>
> For FPGA work? Engineer. My hobby type work is usually with other stuff.
>
> But I must ask: what difference does that make? Had I responded
> "hobbyist" for FPGA work would my opinion have meant less to you? Why?

I wasn't asking about your title, or whether you were getting paid. I was
asking about your mindset -- how you approach doing a design.

I apologize in advance -- I'm really not trying to sound elitist here -- but
if you need "many" iterations to debug a simple design (your word, not mine),
then what you are doing is not engineering. I have done and have seen others
do very complex designs, including FPGAs with tens of thousands of gates and
large PCBs with hundreds of ICs, in just 1-3 iterations.

Frankly, the fact that you don't believe that this is even possible worries
me. How many other developers share your mindset? Are we as a society
gradually losing this level of technical skill?

-- Dave Twee

2011\10\14@153810 by Herbert Graf

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On Fri, 2011-10-14 at 15:01 -0400, Dave Tweed wrote:
> I apologize in advance -- I'm really not trying to sound elitist here -- but
> if you need "many" iterations to debug a simple design (your word, not mine),

A "simple" design in the professional world rarely is.

For example, yes, this chip is "simple". But chances are you are going
to have it on a board with MANY other parts, designed by MANY other
individuals, depending on MANY docs, with likely MANY architectural
changes (been there, done that).

If your design is "one man" and you are the customer then I can agree
with you, if you spend the time to do it perfectly on the onset chances
are you won't need many iterations.

In the real world, in my experience, rarely is a design one man, and
rarely does your customer know what they want. Chances are the specs
will change. Other then changes, chances are the specs will be
interpreted by one design team one way, and by another another way (I've
seen it many times, in one case the docs specified a protocol in such a
way that it would be easy to interpret how the chip worked in two
completely different and incompatible ways, one design team interpreted
it one way, the other the other way, in the end, the design would have
been deadlocked had the mistake not been caught).

> then what you are doing is not engineering. I have done and have seen others
> do very complex designs, including FPGAs with tens of thousands of gates and
> large PCBs with hundreds of ICs, in just 1-3 iterations.

Actually, it's VERY engineering, here's why:

With boards, I agree with you (I usually work on designs with many FPGAs
on a board, so millions of gates is the result). The point is it's VERY
hard to change a board after it's fabbed. So a larger amount of
engineering effort is put into the board so that there are zero errors.

It's a tradeoff. If your design CAN be changed, then getting it in a
physical form is accelerated, since problems can be fixed after the
fact. If your design is hard to change (i.e. a OTP part, or a PCB) then
ALOT more up front engineering time will be spent to ensure everything
is correct.

That is engineering: weighing the pros and cons and making a
compromise.
For me, adding a OTP part to a board is not worth it, given the
thousands of alternatives that don't have that limitation. I understand
others might find this part useful, for me, no thanks.

TTYL

2011\10\14@153832 by V G

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On Fri, Oct 14, 2011 at 2:00 PM, Bob Ammerman <RemoveMEpicramspamTakeThisOuTroadrunner.com> wrote:

> From: "V G" <x.solarwind.xEraseMEspam.....gmail.com>
> > One time programmable is a dealbreaker :(
>
> Not at 0.24 each.
>
> Assume you spend as little as 10 minutes coming up with each version of the
> chip.
>
> An hours worth of chips is then less than a buck and a half.
>
> Your time is worth a lot more than that!
>

I mean personally. It's a dealbreaker for me. But I don't think I'd ever use
these anyway. I'd consolidate my requirements to a CPLD.

32 macrocell Coolrunner II is $1.25 in singles

2011\10\14@154001 by Herbert Graf

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On Fri, 2011-10-14 at 14:00 -0400, Bob Ammerman wrote:
> From: "V G" <EraseMEx.solarwind.xspamgmail.com>
> > One time programmable is a dealbreaker :(
>
> Not at 0.24 each.
>
> Assume you spend as little as 10 minutes coming up with each version of the
> chip.
>
> An hours worth of chips is then less than a buck and a half.

Nope. This isn't a DIP part that fits in an easy to find socket. It's a
VERY tiny, leadless part. So either you'll be soldering and desoldering
every single iteration, or you'll get a custom (read: EXPENSIVE) socket
fabbed. Either way, lots more then 10 minutes an iteration in time or
actual money.

TTYL

2011\10\14@160903 by Mark Rages

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On Fri, Oct 14, 2011 at 1:39 PM, Herbert Graf <RemoveMEhkgrafEraseMEspamEraseMEgmail.com> wrote:

> Nope. This isn't a DIP part that fits in an easy to find socket. It's a
> VERY tiny, leadless part. So either you'll be soldering and desoldering
> every single iteration, or you'll get a custom (read: EXPENSIVE) socket

$12 is EXPENSIVE?

http://www.silego.com/buy/index.php?main_page=product_info&cPath=38&products_id=257



-- Regards,
Mark
markrages@gmai

2011\10\14@205625 by speff

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Quoting Mark Rages <RemoveMEmarkragesspam_OUTspamKILLspamgmail.com>:

> On Fri, Oct 14, 2011 at 1:39 PM, Herbert Graf <RemoveMEhkgrafTakeThisOuTspamspamgmail.com> wrote:
>
>> Nope. This isn't a DIP part that fits in an easy to find socket. It's a
>> VERY tiny, leadless part. So either you'll be soldering and desoldering
>> every single iteration, or you'll get a custom (read: EXPENSIVE) socket
>
> $12 is EXPENSIVE?
>
> http://www.silego.com/buy/index.php?main_page=product_info&cPath=38&products_id=257

Extremely reasonable, and with free development software (assuming it's not
totally awful) and cheap dev boards it looks like a very enticing offering
for just about any commercial application. The software doesn't have  to be all that good, since the chips are so very simple.

Of course the chip is only available from this (new?) company, and  that implies a certain degree of risk. I would say that outweighs  whether it costs a few hundred dollars more or less to develop a  product, which is usually down
in the noise along with courier costs and so on.

Best regards,
Spehro Pefhany

2011\10\14@214311 by William \Chops\ Westfield

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On Oct 14, 2011, at 12:01 PM, Dave Tweed wrote:

> Are we as a society gradually losing this level of technical skill?

Probably.  People can't write near-perfect fortran on a coding pad,  suitable to be handed off to a cardpunch operator, either.

What's the world coming to!

BillW

2011\10\15@001551 by Jason White

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Any see This ?

"GreenPAK Application Notes
 Prototyping GreenPAK 1 ICs in a PDIP Socket
(pdf)<www.silego.com/uploads/Silego_GreenPAK1_ApplicationNote_AN0001..pdf>
"

not a very thorough document, but its a very simple solution ...

-- Jason Whit

2011\10\15@012437 by William \Chops\ Westfield

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On Oct 14, 2011, at 9:04 AM, Herbert Graf wrote:

>> Only downside I can see is that it's OTP

That and the package.  I think I'd be willing to work with an OTP if  it didn't also require soldering to and using up a PCB for each  iteration (or each couple iterations.)  $95 sockets are not a  solution...

Are there any similar devices with better "usability"?  I often wished  for some simple PLD-like device in a low-pin-count package with some  'fixed' and buried functionality like these seem to have (counters,  etc), but the low-pin-count devices seem to be very 'one generic  macrocell per pin', and the embedded higher level functions don't show  up till you get to the high pin count parts.

BillW

2011\10\15@045008 by Mike Harrison

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On Fri, 14 Oct 2011 22:24:16 -0700, you wrote:

>
>On Oct 14, 2011, at 9:04 AM, Herbert Graf wrote:
>
>>> Only downside I can see is that it's OTP
>
>That and the package.  I think I'd be willing to work with an OTP if  
>it didn't also require soldering to and using up a PCB for each  
>iteration (or each couple iterations.)  $95 sockets are not a  
>solution...

Why not? - actually the sockets are $18, but even if they were $95, that cost is a pretty trivial
part of development cost if your product is cost-sensitive enough to be looking at $0.18 parts as an
alternative to a $0.40 MCU
>Are there any similar devices with better "usability"?  I often wished  
>for some simple PLD-like device in a low-pin-count package with some  
>'fixed' and buried functionality like these seem to have (counters,  
>etc), but the low-pin-count devices seem to be very 'one generic  
>macrocell per pin', and the embedded higher level functions don't show  
>up till you get to the high pin count parts.
>

The only other parts I'm aware of  are the logic block Microchip  have added to a few new PICs

2011\10\15@081309 by William \Chops\ Westfield

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On Oct 15, 2011, at 1:50 AM, Mike Harrison wrote:

>> That and the package.  I think I'd be willing to work with an OTP if
>> it didn't also require soldering to and using up a PCB for each
>> iteration (or each couple iterations.)  $95 sockets are not a
>> solution...
>
> Why not? - actually the sockets are $18, but even if they were $95,  
> that cost is a pretty trivial
> part of development cost if your product is cost-sensitive enough to  
> be looking at $0.18 parts as an
> alternative to a $0.40 MCU

Where did you find $18 sockets?  That wouldn't be so bad.  (they'd  have to be sockets, not adapter boards that you solder to!)  (Ah, I  see.  From Silego themselves!  Just order both development kits and a  spare socket in each size.  Should be interesting.

Also, it appears that these are actually RAM-based logic, with the OTP  backing up the RAM.  Using their (cheap) emulation/programming board,  you can apparently load up the RAM as many times as you want, do some  testing via their tools and external connections, and have a jolly old  time trying things out
http://www.eetimes.com/design/programmable-logic/4218821/Silego-s-GreenPAK---Design-and-program-a-custom-chip-in-minutes    I wonder if it's possible to put a small battery or large cap on a  DIP adaptor board, and have a short-term part that can be moved from  one place to another?  An interesting project.

And they have a Mac version of their developement software.  how could  I resist!

BillW

2011\10\15@133629 by Dwayne Reid

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Many thanks for the link and information.  For the life of me, I've NOT been able to see where to grab the data-sheets from on their website.  Has anyone else been able to find data-sheets?  Links would be appreciated.

Having these be RAM-based devices means that I am definitely going to be ordering at least the 5V dev kit and some extra sockets.  Using the OTP part to load the RAM cells upon bootup is brilliant - the OTP can be as slow as it wants to be without affecting performance.  And, as you mention, because its RAM-based, you can iterate as often as you want or need without having to replace the chip.

Brilliant!

dwayne


At 06:13 AM 10/15/2011, William \"Chops\" Westfield wrote:

{Quote hidden}

-- Dwayne Reid   <EraseMEdwaynerspamspamspamBeGoneplanet.eon.net>
Trinity Electronics Systems Ltd    Edmonton, AB, CANADA
(780) 489-3199 voice          (780) 487-6397 fax
http://www.trinity-electronics.com
Custom Electronics Design and Manufacturing

2011\10\15@134725 by Sean Breheny

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I think that both extremes are rarely good.. in other words, if you
just "cut and try" constantly without any real analysis of your design
up-front, then the end result is likely to be full of holes and hidden
bugs, and the approach is just intellectually sloppy. On the other
hand, if you spend huge amounts of time to get it all correct prior to
the first actual test, then the total development time is likely to be
much longer than if you had included a small number of
analyze-design-test-debug cycles.

I remember once doing a design (back in high school) where I was
writing code for a microcontroller (actually an 8088 in minimal mode)
and the code was going to be written into an EPROM by someone else,
after which it had to work the first time because I didn't have an
EPROM programmer or eraser. The code was only about 50 instructions
long. I spent about 1 full week simulating and analyzing it before I
gave it to the guy to program into the EPROM for me. It did indeed
work the first time, but the amount of effort was about 1 hour per ASM
instruction :) That really cannot be extended to much larger projects.

On Fri, Oct 14, 2011 at 9:43 PM, William "Chops" Westfield
<RemoveMEwestfwKILLspamspammac.com> wrote:
{Quote hidden}

>

2011\10\15@140308 by Marcel Duchamp

picon face
On 10/15/2011 10:36 AM, Dwayne Reid wrote:
> Many thanks for the link and information.  For the life of me, I've
> NOT been able to see where to grab the data-sheets from on their
> website.  Has anyone else been able to find data-sheets?  Links would
> be appreciated.

Here's the link for one of them:
http://www.silego.com/uploads/Products/product_123/xSLG46200r108_09192011.pdf

I had the same reaction as you: where the heck are the datasheets?  They have the usual Adobe pdf icon fairly small, around halfway down the page.  Below that is one for errata as well.

When in doubt, type ctrl-u to see the page source, ctrl-f to find text, "pdf" and enter and see if any mention of pdf occurs on the page. Or cntrl-f on the actual page for "datasheet". Of course, you should not have to do this at all.

These do look like interesting parts.


>
> Having these be RAM-based devices means that I am definitely going to
> be ordering at least the 5V dev kit and some extra sockets.  Using
> the OTP part to load the RAM cells upon bootup is brilliant - the OTP
> can be as slow as it wants to be without affecting performance.  And,
> as you mention, because its RAM-based, you can iterate as often as
> you want or need without having to replace the chip.
>
> Brilliant!
>
> dwayne

2011\10\15@141238 by Scott Dattalo

face
flavicon
face
> Many thanks for the link and information.  For the life of me, I've
> NOT been able to see where to grab the data-sheets from on their
> website.  Has anyone else been able to find data-sheets?  Links would
> be appreciated.

http://www.silego.com/uploads/Products/product_123/xSLG46200r108_09192011.pdf

2011\10\15@171540 by William \Chops\ Westfield

face picon face

On Oct 15, 2011, at 10:36 AM, Dwayne Reid wrote:

> I've NOT been able to see where to grab the data-sheets from on their
> website.  Has anyone else been able to find data-sheets?  Links would
> be appreciated.

www.silego.com/uploads/Products/product_123/xSLG46200r108_09192011.pdf
http://www.silego.com/uploads/Products/product_194/xSLG46400r053_09192011.pdf

The little PDF icon next to the "Buy now" in the table of part numbers  (or it WOULD be a table if it had more than one part in it...)

BillW

2011\10\16@121918 by Electron

flavicon
face

>On 10/15/2011 10:36 AM, Dwayne Reid wrote:
> Many thanks for the link and information.  For the life of me, I've
> NOT been able to see where to grab the data-sheets from on their
> website.  Has anyone else been able to find data-sheets?  Links would
> be appreciated.

This is even better, here you can find also the software to play with,
and more:

http://www.silego.com/index.php?page=support


> Having these be RAM-based devices means that I am definitely going to
> be ordering at least the 5V dev kit and some extra sockets.  Using
> the OTP part to load the RAM cells upon bootup is brilliant - the OTP
> can be as slow as it wants to be without affecting performance.  And,
> as you mention, because its RAM-based, you can iterate as often as
> you want or need without having to replace the chip.

Sorry, I'm not sure I do understand: is the OTP bypassable during design?

Or am I misunderstanding you?

Cheers,
Mario



> Brilliant!
>
> dwayne

2011\10\16@134544 by William \Chops\ Westfield

face picon face

On Oct 16, 2011, at 9:18 AM, Electron wrote:

> is the OTP bypassable during design?

It appears that with the board they sell ($50 including 50 samples),  you can download a design, probe it with assorted signal generators  while looking at it with a scope/etc (signal generators built into the  board, but you supply the scope?), and decide whether it's behaving  OK.  If so, you then commit the design to the OTP (otherwise you try  again without burning the OTP.)  If you lose power, the RAM cells go  away, so you can't exactly plug it into your actual circuit (except  perhaps via header-style pins on the board), but it's not like you  have to program and pray (like with PALs...)

BillW

2011\10\16@152457 by smplx

flavicon
face

has anybody else noticed this?

"SILEGO" <---> "Si LEGO"


Regards
Sergio Masc

2011\10\17@150821 by Electron

flavicon
face

Cool, thanks.

Now do I need it? I downloaded the app to simulate some design.. it's
hard though to find a REAL use for me right now (I wish it had more
stuff inside, then..). But it's cheap.

By the way, the $49 GreenPAK2 devkit has 8 weeks of lead time already.. :P


At 19.45 2011.10.16, you wrote:
{Quote hidden}

>

2011\10\17@163843 by V G

picon face
On Mon, Oct 17, 2011 at 3:07 PM, Electron <electron2k4STOPspamspamspam_OUTinfinito.it> wrote:

> Cool, thanks.
>
> Now do I need it? I downloaded the app to simulate some design.. it's
> hard though to find a REAL use for me right now (I wish it had more
> stuff inside, then..). But it's cheap.
>
> By the way, the $49 GreenPAK2 devkit has 8 weeks of lead time already.. :P
>
>
That's (personally) pretty disappointing. That, and the minimum quantity of
100 chips.

However, loving the Xilinx CPLDs. Easy to program, SUPER cheap, and
awesomely functional

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