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'[PIC]24LC64 I2C memory?'
2006\04\10@221818 by Pat Smith

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Ayone got any example code to read and write to this 64K memory.  
This is a home learning  project for fun.


2006\04\10@224647 by Jinx

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> Ayone got any example code to read and write to this 64K memory.  
> This is a home learning  project for fun.

Using what ? Bit-bang or MSSP ?

2006\04\10@232709 by Pat Smith

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Bit bang

-----Original Message-----
From: spam_OUTpiclist-bouncesTakeThisOuTspammit.edu [.....piclist-bouncesKILLspamspam@spam@mit.edu] On Behalf Of
Jinx
Sent: Monday, April 10, 2006 9:46 PM
To: Microcontroller discussion list - Public.
Subject: Re: [PIC]24LC64 I2C memory?



> Ayone got any example code to read and write to this 64K memory.  
> This is a home learning  project for fun.

Using what ? Bit-bang or MSSP ?

2006\04\10@235101 by Herbert Graf

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On Mon, 2006-04-10 at 21:18 -0500, Pat Smith wrote:
> Ayone got any example code to read and write to this 64K memory.  
> This is a home learning  project for fun.

My carmon project reads and writes to a 24 series EEPROM in bit bang
mode:

http://repatch.dyndns.org:8383/pic_stuff/carmon

Thanks, TTYL

2006\04\11@001209 by Bob Axtell

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Here is a piece of working bit-banged code for FM24C256 (32X x 8).
This came from PIC16F88 but it will work anywhere. Ripped right
out of active code.

; general equates
SDA        equ    1
SCL        equ    2
; slave address
FRAM        equ    h'A0'   ;FM24CL64 slave address
; bunch of temp registers
tmp8, etc etc
;*******************************************
;  I2C Routines: Note: operates in MAIN
; 1. tries 4 times before abandoning the pass
; 2. Works on any PIC12/PIC16/PIC18 port
;    that uses TRIS?
; 3. This is idealized for RAMTRON devices; for
;    MicroChip EEROM devices, allow 4mS after
;    writing the byte or group of bytes. There
;    are restrictions about how many bytes can
;    be written, and what the addresses have to
;   be. Read datasheet closely or use Ramtron
;  devices.
;*******************************************
;*******************************************
;  I2C Write Routines
;*******************************************
f2wrn:
   movwf    tmp8
   movlw    FRAM            ;FRAM Selection Bits
   movwf    sadr
   movf    FSR,w
   movwf    h24fsr
   movf    tmp8,w
;*******************************************
; write w bytes fr @FSR to device @HL_bytes
;*******************************************
   bank0
   bsf    flags,i2cFLG    ;tells interrupt that I am using SCK
   clrwdt
   movwf   i2cnt
   call    Bstrtx          ; Generate START bit
   goto    i2wry
i2wlp:
   call    restart
   bcf    flags,i2
i2wry:
   movf    sadr,W
   call    TX              ; Output SLAVE data address
       btfsc   flags,i2        ; Check for error
       goto    i2wlp           ; wait until write cycle done
   movf    INTCON,w
   movwf    tmp8
   bcf    INTCON,GIE
   movf    H_byte,w        ; Put internal HI address onto bus
   call    TX              ; Output WORD address. Check ACK.
       btfsc   flags,i2        ; Check for error
       goto    BSTOPw          ; Generate STOP bit
   movf    L_byte,w        ; Put internal LO address onto bus
   call    TX              ; Output WORD address. Check ACK.
       btfsc   flags,i2        ; Check for error
       goto    BSTOPw          ; Generate STOP bit
       movf    i2cnt,w
       movwf   h24cnt
i2wr1:  
   movf    INDF,w          ; Move DATA
   call    TX              ; Output DATA and detect acknowledgement
       btfsc   flags,i2        ; Check for error
       goto    BSTOPw          ; Generate STOP bit
   incf    FSR,f
       decfsz  h24cnt,f
   goto    i2wr1
   call    BSTOP           ; Generate STOP bit
   goto    i2exit
;********************************************
;      I2C Read Routines
;********************************************
f2rdn:
   movwf    tmp8
   movlw    FRAM               ;FRAM select
   movwf    sadr
   movf    tmp8,w
;********************************************
; read w bytes to @FSR fr device @H_byte/L_byte
;*******************************************
i2rdn:
       bank0
   bcf    flags3,write
   bsf    flags,i2cFLG
   clrwdt
   movwf   i2cnt
   call    Bstrtx          ; Generate START bit
   goto    i2rdy
i2rlp:
   call    restart
   bcf    flags,i2
i2rdy:
   movf    sadr,w
   call    TX              ; Output SLAVE data address
       btfsc   flags,i2        ; Check for error
       goto    i2rlp           ; wait until write cycle done
   movf    INTCON,w
   movwf    tmp8
   bcf    INTCON,GIE
   movf    H_byte,w        ; Put HI data address onto bus
   call    TX              ; Output WORD address. Check ACK.
       btfsc   flags,i2        ; Check for error
       goto    BSTOPr          ; Generate STOP bit
   movf    L_byte,w        ; Put HI data address onto bus
   call    TX              ; Output WORD address. Check ACK.
       btfsc   flags,i2        ; Check for error
       goto    BSTOPr          ; Generate STOP bit
;
   call    restart
       movf    sadr,w          ; slave adr
    iorlw    1               ; Specify READ mode (R/W = 1)
   call    TX              ; Output SLAVE address
       btfsc   flags,i2        ; Check for error
       goto    BSTOPr          ; Generate STOP bit
       movf    i2cnt,w
       movwf   h24cnt
i2rd1:
; RECEIVE eight data bits subroutine
; exit = w has data
   bsf     tmp2,3          ; 8 bits of data
RXLP:
   call    BITIN           ; get data
       rlf     tmp,f           ; install bit, LS last
   decfsz  tmp2,f          ; 8 bits?
   goto    RXLP
       clrwdt
       bsf     status,c        ; try no ack
       decfsz  h24cnt,w        ; last one?
       bcf     status,c        ; needs ack
   call    BITOUT      
       movf    tmp,w           ; data ready
   movwf   indf            ; Save data into buffer
   incf    fsr,f        ; next char
       decfsz  h24cnt,f
   goto    i2rd1  
   call    BSTOP           ; Generate STOP bit
i2exit:
   btfsc    tmp8,GIE
   bsf    INTCON,GIE
   return
; TRANSMIT 8 data bits subroutine in tmp
TX:    
   movwf    tmp
   bsf     tmp2,3          ; 8 bits of data
TXLP:  
   rlf     tmp,f           ; Shift data bit out.
   call    BITOUT          ; Serial data out
   decfsz  tmp2,f          ; 8 bits done?
   goto    TXLP            ; No.
   clrwdt
   call    BITIN           ; Read acknowledge bit
       btfsc   status,c        ; acknowledgement?
       bsf     flags,i2        ; not received
   return
; Single bit receive from I2C to PIC
; data in carry
BITIN:  
   bank1
   bsf     trisa,SDA       ; Set SDA for input
       bk0
   bsf     porta,SCL       ; Clock high
   bcf    status,c        ; def=0 (has ack)
   btfsc   porta,SDA       ; Read SDA pin, for ACK low
   bsf     status,c        ; no ack detected
   call    wt_
       bcf     porta,SCL       ; finish bit in case
   goto    wt_
;  Single bit data transmit from PIC to I2C
;  Input= carry bit
BITOUT:
   btfss   status,c
   goto    BIT0
       bsf     porta,SDA       ;drive it high
   goto    CLK1
BIT0:  
   bcf     porta,SDA       ;drive low
CLK1:  
   bank1
   bcf     trisa,SDA       ; Output bit 0
       bk0
   bsf     porta,SCL
   call    wt_
   bcf    porta,SCL       ;on low
   goto    wt_
; start but also set loop count
Bstrtx:
   clrf    h24lp
   bsf     h24lp,2           ;4x max
Bstrty:
       bcf     flags,i2          ;no error yet
   clrf    tmp2
;   START bit generation routine
;Generate START bit (SCL is high while SDA goes from high to low transition)
; quiscent state is both high....
BSTART:
       bsf     porta,SCL    ;in case not high
   bank1
       bcf     trisa,SDA       ;both driven
       bk0
   call    wt_
       bcf     porta,SDA       ;SDA=lo = START CDX
       call    wt_
       bcf     porta,SCL
; for 8Mhz clock... For 4Mhz, remove the first one;
; for 20Mhz clock, double the this wait
wt_:
       goto     $+1
   goto    $+1
   return
; HALFSTART
RESTART:
; a RESTART, i.e. no STOP, followed by START
; upon entry SCL is always low.
   bsf    porta,SDA    ;force hi
   bank1
       bcf     trisa,SDA       ;no stop condx
   bank0
   bsf    porta,SCL    ;both now hi
   call    wt_      
   bcf    porta,SDA
   call    wt_
   bcf    porta,SCL    ;SDA lo then SCL lo START
   goto    wt_
; write stop with test first
BSTOPw:
   call    BSTOP
       movf    h24lp,f
       btfsc   status,z
       goto    i2exit
       decf    h24lp,f
   movf    h24fsr,w
   movwf    FSR
       call    Bstrty
       goto    i2wry
; read stop with test first
BSTOPr:
   call    BSTOP
       movf    h24lp,f
       btfsc   status,z
       goto    i2exit
       decf    h24lp,f
   movf    h24fsr,w
   movwf    FSR
       call    Bstrty
       goto    i2rdy
;  STOP bit generation routine
;Generate STOP bit (SDA goes from low to high during SCL high state)
;and check bus conditions.
BSTOP:
; SCL is now low, always.
   bcf    porta,SDA    ;force low
   bank1
       bcf     trisa,SDA
   bk0            ;both low
   call    wt_
       bsf     porta,SCL     ;scl high
       call    wt_
       bsf     porta,SDA          ;SDA=hi = STOP CDX
       call    wt_
   bk1
       bsf     trisa,SDA    ;SDA=OC
   bk0
   bcf    flags,i2cFLG
       return

HOLLER if you missed anything.

--Bob

Pat Smith wrote:

{Quote hidden}

>

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