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'[PIC] 18LF6722 SPI Problem'
I'm running a 6722 SPI in master mode 01. I verify with the ICD-2 that
both CKP and CKE are zero. For most of the transmitted byte, data properly
changes on the positive edge and is stable on the negative edge. HOWEVER,
on the LSB (last transmitted), the bit is properly set up on the positive
edge, but drops to zero on the negative edge (or about 200ns after the
negative edge). This may not be meeting the hold time requirements of the
device we're driving. I find no errata on this device showing this problem
with the MSSP module. Has anyone else experienced this? Is there a
workaround (or should I go to software generated SPI)?
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