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'[PIC]: very special request'
2003\04\24@141436 by Olin Lathrop

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{Quote hidden}

I only received 3 of the rev C0 18F252 parts myself, and I really can't
afford to part with any of them.  One is at a customer, another in a
duplicate circuit here to support the one at the customer, and the third
is being tested right now in a different project.  Also I got these for
free as samples, so it wouldn't be right for me to sell them to someone
else.

It helps to have a good relationship with the people in your local
Microchip office, but I understand that is difficult or impossible for a
student.  If you really can't get any rev C0 18F252 parts, then I think
your best options are:

1  -  Figure out how to use a single interrupt priority level.

2  -  Use one of the newer 18F parts that doesn't have the interrupt
priority bug.  However beware that some of these have other problems in
that they don't work at the full specified speed.  I consider the 18F1320,
for example, to be a 20MHz device until Microchip fixes this problem.

3  -  Use separate PICs to handle different interrupt conditions and have
them all somehow (IIC, SPI ?) talk to a central PIC that collects the
data.

Sorry I couldn't be more helpful.


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2003\04\24@150021 by Chris Loiacono

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> > Some weeks ago, I wrote to the Piclist because I needed help
> > about asynchronous interrupt. You said to me that the 18's family
> > has 2 levels of interrupt, but unfortunately, there is a bug with
> > that feature which have been fixed very recently.

Forgive me if I have missed something in the earlier thread, but I have an
entire product line that uses multiple interrupt priorities on PIC18's. (see
http://www.auto-serv.com/products/index.php3 )
We here are in doubt that this ever was a real bug and have been using this
feature for 2+ years w/o any problems. This has been our experience with 18C
& F 2's & 4's.
I have an excess of C442's in PLCC44 if that's of any help. I might even
have a few F452's in TQFP, but these can be had just about anywhere - I buy
from a myriad of vendors and have never had a problem, although I have
limited experience with 18F/C2's. I do seem to recall these also running the
same priority interrupts well also though.......

CHris

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2003\04\24@152405 by Hazelwood Lyle

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>> about asynchronous interrupt. You said to me that the 18's family
>> has 2 levels of interrupt, but unfortunately, there is a bug with
>> that feature which have been fixed very recently.
....
{Quote hidden}

One good possibility is the 18F458.
It should be pin compatible, just don't enable the CAN port.
I am using these successfully at 39.3216 Mhz. Haven't tried 40 yet.

I have seen no mention of either the interrupt priority bug or a
clock speed bug in the errata sheet for this chip (80134C.pdf)

These chips should be available from the usual places.
Digi-Key currently has DIP,PLCC, and TQFP packages in stock for
singles pricing from $10.30 to $11.53 depending on package.

Good Luck
Lyle

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2003\04\24@160136 by Olin Lathrop

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> Forgive me if I have missed something in the earlier thread, but I have
> an entire product line that uses multiple interrupt priorities on
> PIC18's. (see http://www.auto-serv.com/products/index.php3 )
> We here are in doubt that this ever was a real bug and have been using
> this feature for 2+ years w/o any problems. This has been our
> experience with 18C & F 2's & 4's.
> I have an excess of C442's in PLCC44 if that's of any help. I might even
> have a few F452's in TQFP, but these can be had just about anywhere - I
> buy from a myriad of vendors and have never had a problem, although I
> have limited experience with 18F/C2's. I do seem to recall these also
> running the same priority interrupts well also though.......

I don't know how likely the bug is to occur, but if Microchip admits to a
problem I take it seriously.  Note that multiple priority interrupts
aren't completely broken, just high priority asynchronous interrupts when
low priority interrupts are also used.


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2003\04\24@160349 by Olin Lathrop

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> One good possibility is the 18F458.
> It should be pin compatible, just don't enable the CAN port.
> I am using these successfully at 39.3216 Mhz. Haven't tried 40 yet.

I haven't checked, but don't these have the same bug as the 18Fxx2 chips?


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2003\04\24@163742 by Lyle Hazelwood

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>> One good possibility is the 18F458.
>> It should be pin compatible, just don't enable the CAN port.
>> I am using these successfully at 39.3216 Mhz. Haven't tried 40 yet.

>I haven't checked, but don't these have the same bug as the 18Fxx2 chips?

I have not seen any problems like this in my own work.
Admittedly, I'm still in the prototyping stages, but I do have
what I would consider to be asynch high priority interrupts,
along with a few low priority interrupts, and so far all the
problems have been directly attributed to my lack of mental
organization. 8^)

I am using the upper interrupts to time stamp IR transitions, and
so far the data has been quite repeatable.

I checked the datasheets to be sure, and there is no mention of
interrupt related bugs in the 18Fxx8 chips.

I am also clocking at 39.3216 Mhz, and haven't had any trouble so far.
I even have switched back and forth between HS and HSPLL on successive
flashes to verify my programs ability to read the config bits and scale
timers and BRGs accordingly, and the switch seems quite transparent.

Minor point of info for other users: MPLAB does not "emulate" reading
of the CONFIG registers, so I had to test that code in real hardware.
I plan on making all of my boards for this project with 9.8304 Mhz
crystals, then adding an HSPLL config only on boards that require
more processing power. Kinda cool, I think.

I'm not yet good enough at PICs to be an authority. My word on this
is not to be taken as final and definite proof of anything.

Anyway, I've just offered what works for me.

Lyle

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2003\04\24@170425 by Robert Reimiller

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On Thu, 24 Apr 2003 16:32:04 -0400, you wrote:
>I am using the upper interrupts to time stamp IR transitions, and
>so far the data has been quite repeatable.
>
Thats funny, that's what I use the high priority interrupt on one of
my PIC18F452 projects. Seems to work fine even with other services
using the low priority interrupt.

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2003\04\24@180905 by Olin Lathrop

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> I checked the datasheets to be sure, and there is no mention of
> interrupt related bugs in the 18Fxx8 chips.

Such bugs are not listed in the data sheet, but rather in a separate
"errata" document.  I just checked the lastest errata sheets and you are
right, the bug is listed for the 18Fxx2 but not for the 18Fxx8.


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2003\04\24@184232 by Bob Ammerman

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Aren't the timer synchronous interrupts. If so, then the bug doesn't apply
IIUC.

Bob Ammerman
RAm Systems

{Original Message removed}

2003\04\24@185637 by Lyle Hazelwood

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>Aren't the timer synchronous interrupts. If so, then the bug doesn't apply
>IIUC.

>Bob Ammerman
>RAm Systems

In my case, the interrupt is from INT0 or INT1, depending on the
IR frequency. On each interrupt, I capture the 16 bit value of
TMR3, then reset the timer. I also reverse the edge detect for
the associated input so I can watch it coming and going.

Since the IR Detectors are not "clocked" by the PIC, I think that
counts as asynchronous. Please correct me if I am mistaken.

I end up with a table of periods between each edge from the IR
signal. The fun part is applying any number of decoders to the data to
try and decipher the format, device, and key pressed.

If it weren't for info from Wagners site, I wouldn't even try to
do the decoding part.

Thanks Wagner!

Lyle

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2003\04\24@210718 by Chris Loiacono

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That's funny because local mchip rep said this was bogus some time ago, and
now the Errata doc apears!!! Yes, now I believe!
>
> > I checked the datasheets to be sure, and there is no mention of
> > interrupt related bugs in the 18Fxx8 chips.
>
> Such bugs are not listed in the data sheet, but rather in a separate
> "errata" document.  I just checked the lastest errata sheets
> and you are
> right, the bug is listed for the 18Fxx2 but not for the 18Fxx8.

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