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'[PIC]: 16F6871 EEPROM write hangs no longer but no'
2001\01\16@101104 by Hardware Engineering

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OK...good news is that it does not hang...yet does not appear to be working
still...hard to tell if its the read or write of course



WRITEEE:
       bsf     STATUS,RP0      ; set up EEADR and EEDATA first
       bcf     INTCON, GIE     ; disable interrupts temporarily
       clrf    EECON1                
       bsf     EECON1,WREN     ; enable write
       movlw   H'55'           ; magic sequence
       movwf   EECON2              
       movlw   H'AA'                  
       movwf   EECON2              
       bsf     EECON1,WR  
       bsf     INTCON, GIE     ; reenable interrupts
       bcf     EECON1, WREN    ; disable EEPROM write
         
EELOOP:
       btfsc   EECON1,EEIF       ; wait for WR to go low
       goto    EELOOP          ; not yet
       bsf     EECON1,WREN            
       bcf     EECON1,EEIF     ; clear the interrupt flag
       bcf     STATUS,RP0      ; return to page 0
       return              


READEE:
       movwf   EEADDR          ; set up eeprom address from W
       bsf     STATUS,RP0      ; change to page 1
       bsf     EECON1,RD       ; set the read bit
       bcf     STATUS,RP0      ; back to page 0
       movf    EEDATA,W        ; return value in W
       return

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2001\01\16@104310 by Michael Rigby-Jones

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You should clear the EEPGD bit before setting the RD bit in your READEE
function.

Why not use the routines in the data sheet?  They seem to work ok.

Mike

> {Original Message removed}

2001\01\16@104337 by Simon Nield

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anon:
>still...hard to tell if its the read or write of course

easy one to solve:
1 - comment out the writing bit, and write some pattern into the flash with the programmer/ icd and
see if it reads back correctly.
2 - or comment out the reading bit, write some pattern into the flash using your code and read it
back on the icd.

Regards,
Simon

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2001\01\16@104636 by Drew Vassallo

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>WRITEEE:
>         bsf     STATUS,RP0      ; set up EEADR and EEDATA first
>         bcf     INTCON, GIE     ; disable interrupts temporarily
>         clrf    EECON1

Not quite sure why you clear this register.  But ok.

{Quote hidden}

         ^^^^^
Apparently you didn't read my message carefully enough.  It should be btfss
not btfsc.  Your write cycle was probably not complete by the time you ended
the write sequence and returned.

{Quote hidden}

Everything else looks ok.

--Andrew
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2001\01\16@164751 by Tony Nixon

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Hardware Engineering wrote:
>
> OK...good news is that it does not hang...yet does not appear to be working
> still...hard to tell if its the read or write of course
>
> WRITEEE:
>         bsf     STATUS,RP0      ; set up EEADR and EEDATA first
>         bcf     INTCON, GIE     ; disable interrupts temporarily
>         clrf    EECON1
>         bsf     EECON1,WREN     ; enable write
>         movlw   H'55'           ; magic sequence
>         movwf   EECON2
>         movlw   H'AA'
>         movwf   EECON2
>         bsf     EECON1,WR
>         bsf     INTCON, GIE     ; reenable interrupts
>         bcf     EECON1, WREN    ; disable EEPROM write

You have disabled the EEPROM write just after starting the write process
and are not looking at RAM page 3 for EECON1/2

> EELOOP:
>         btfsc   EECON1,EEIF       ; wait for WR to go low
>         goto    EELOOP          ; not yet
>         bsf     EECON1,WREN
>         bcf     EECON1,EEIF     ; clear the interrupt flag
>         bcf     STATUS,RP0      ; return to page 0
>         return

Try this


WRITEEE:
       bsf     STATUS,RP0      ; set up EEADR and EEDATA first
       bsf     STATUS,RP1      ; RAM page 3
       bcf     INTCON, GIE     ; disable interrupts temporarily
       clrf    EECON1
       bsf     EECON1,WREN     ; enable write
       movlw   H'55'           ; magic sequence
       movwf   EECON2
       movlw   H'AA'
       movwf   EECON2
       bsf     EECON1,WR
       bsf     INTCON, GIE     ; reenable interrupts

EELOOP:
       btfsc   EECON1,EEIF     ; wait for WR to go low
       goto    EELOOP          ; not yet

       bcf     EECON1,WREN     ; disable writes
       bcf     EECON1,EEIF     ; clear the interrupt flag  ???
       clrf STATUS             ; return to page 0
       return

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2001\01\16@214903 by Drew Vassallo

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> >         bsf     EECON1,WR
> >         bsf     INTCON, GIE     ; reenable interrupts
> >         bcf     EECON1, WREN    ; disable EEPROM write
>
>You have disabled the EEPROM write just after starting the write process
>and are not looking at RAM page 3 for EECON1/2

From the datasheet:

"The user should keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared by hardware"
...
"After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set."

The problem could be with the RAM page selection, I don't know.  But you
have NOT disabled the EEPROM write after starting the cycle.  You have
disabled the WRITE ENABLE bit, not the WRITE bit.  This is not your problem.

--Andrew
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2001\01\16@215127 by Drew Vassallo

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>         clrf STATUS             ; return to page 0
>         return

I'm not a big fan of using "clrf STATUS" just to select page 0.  Try using
"bcf STATUS, RP0" as a more direct instruction.


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2001\01\16@220603 by Tony Nixon

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Drew Vassallo wrote:
>
> >         clrf STATUS             ; return to page 0
> >         return
>
> I'm not a big fan of using "clrf STATUS" just to select page 0.  Try using
> "bcf STATUS, RP0" as a more direct instruction.
>
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It can't hurt in this case as long as the IRP bit was not specifically
set - just the Z bit will be set = 1.

You will need...

bcf STATUS,RP1
bcf STATUS,RP0

becasue EECON1 & EECON2 are in BANK 3


> "After a write sequence has been initiated, clearing the
> WREN bit will not affect this write cycle. The WR bit will
> be inhibited from being set unless the WREN bit is set."

Fair enough, I missed that point.

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