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'[PIC]: [EE]: Microprocessor internal reset circuit'
2001\04\13@043532 by Roman Black

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David W. Gulley wrote:
>
> Russell McMahon wrote:
>   <SNIP>
> > 5.    What would you think of a processor that behaved like this?
> > I assume that in more normal circuits some of these will sometimes cause
> > problems. These problems would be hard to track down and there cause may
> > remain a mystery indefinitely.
>
>   Short answer, I do not like it!
> I have had similar problems with reset circuits (from various
> manufacturers). In one case, adding bulk capacitance near the device
> *helped*. It seems (in that case) if there were a power droop
> immediately following the device coming out of reset (which happened due
> to everything else "waking up"), the reset logic would shut down
> thinking power had gone *bad*, and it would not come out of reset until
> power was shut down and restored (with faster rise time).


OK, i'll probably get laughed at here but I have
simple software way of reducing power-up hassles
with PICs.

The very first code sets ports to 0 value and then
sets port directions all to OUTPUTS. This holds the
pins low, meaning that they do not ride up with the Vdd
voltage at power on like outputs set high, especially
high outputs into any loads.

If you're wondering why I don't leave them as inputs
during the powerup Vdd rise it is because if they are
low outputs there is no latchup problems. Inputs are
floating, and as the Vdd rises they go through various
stages, which are undefined as the Vdd is not reliable.
As you know with cmos inputs they should be not floated
at unusual voltages. This can cause temporary latchup
which is a big current surge, the worse thing really
during powerup stage.

So as there is no other loads other than the PIC processor
can get to full voltage quickly, it only draws a few mA.
I measure most of my app's powerup times, generally 200mS
is fine. So after 300mS I then set pins to proper in/out
values, reset timers, enable interrupts etc etc.

I also make sure that I don't have pins that CAN'T be
held low, there may be a rare circuit that has pins
like this. That would be bad design really? I've never
done it. :o)
-Roman

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2001\04\13@065301 by Bob Ammerman

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> I also make sure that I don't have pins that CAN'T be
> held low, there may be a rare circuit that has pins
> like this. That would be bad design really? I've never
> done it. :o)
> -Roman

I am working with a circuit that includes a radio transceiver. The
transceiver  has an active-low input line called '/TXON' to turn on the
transmitter.

When I power up this line _must_ remain high until I am ready to transmit
something (the FCC might not be happy with garbage transmissions coming out
as Vdd ramps up).

The pin is connected to a pullup, and I can't very well hold it low.

Your idea in general, however, is a good one. I'd just change it to the
following:

"At reset set all I/Os to whatever state will ensure minimum power draw from
the Vdd power supply whenever and wherever possible."

Note that setting the subject pin HI will reduce current from Vdd (thru the
pullup resistor).

Bob Ammerman
RAm Systems
(contract development of high performance, high function, low-level
software)

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2001\04\13@095056 by David W. Gulley

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Roman Black wrote:
<SNIP>
> OK, i'll probably get laughed at here but I have
> simple software way of reducing power-up hassles
> with PICs.
>
> The very first code sets ports to 0 value and then
> sets port directions all to OUTPUTS. This holds the
> pins low, meaning that they do not ride up with the Vdd
> voltage at power on like outputs set high, especially
> high outputs into any loads.
>
> If you're wondering why I don't leave them as inputs
> during the powerup Vdd rise it is because if they are
> low outputs there is no latchup problems. Inputs are
> floating, and as the Vdd rises they go through various
> stages, which are undefined as the Vdd is not reliable.
> As you know with cmos inputs they should be not floated
> at unusual voltages. This can cause temporary latchup
> which is a big current surge, the worse thing really
> during powerup stage.

However, that first instruction on the PIC is going to occur sometime
AFTER power has risen to some intermediate level and reset (at least to
the PIC) has been released. If the reset initializes the pins to a given
state, that state will be present until your first instruction is
executed. Given a REALLY slow power ramp up (perhaps with a small saw
tooth added) there is a likelihood that various devices in the system
will become "alive" before others and that first instruction may still
be milliseconds from execution. Certainly initializing the pins as you
suggest may help in some environments, but may be insufficient or
imprudent in others.


David W. Gulley
Destiny Designs

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2001\04\13@100103 by Douglas Wood

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How do you run code while Vdd is powering up?

Douglas Wood
Software Engineer
spam_OUTdbwoodTakeThisOuTspamkc.rr.com

Home of the EPICIS Development System for the PIC and SX
http://epicis.piclist.com

{Original Message removed}

2001\04\16@044518 by Roman Black

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Douglas Wood wrote:
>
> How do you run code while Vdd is powering up?

Isn't this a typical PIC startup problem?
The MCLR is referenced to Vdd, so if MCLR is
tied to Vdd they will both rise together, and
the the PIC will start executing code possibly
about 2.5v, anyway well before Vdd reaches 5v.

With some simpler circuits I found it useful to
keep the pins in a *known* state, the best for
my apps is as outputs at 0v. Once the time has
elapsed and you are sure the Vdd has stabilised
you can set the pins as inputs where needed
and start all the other processes.

Someone mentioned that during startup the pins
should be held in whichever state will make the
circuit draw the least current, so Vdd reaches 5v
soonest. This is right, but if they are "high"
outputs they will possibly go through undefined
stages as Vdd rises. I prefer with simple circuits
to design the whole thing so "low" outputs are
best during startup mode ("high" outputs drive
things).

Obviously using a MCLR delay cap or a reset chip
would change everything, but again with a simple
circuit the MCLR cap would cause ICSP problems and
a reset chip adds cost and complexity. This is just
one way of going about a difficult problem.
:o)
-Roman

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