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'[OT] Verilog pSRAM joy'
2011\10\07@182913 by V G

picon face
I would like to share this little slice of happiness with you all. I finally
got the pSRAM on my Nexys 2 board working in asynchronous mode. Can reliably
write and read data. Time to get the logic analyzer working.

Any suggestions would be much appreciated.


module Main(
   input wire clk,
   output wire [7:0] Led,
   input wire [3:0] btn,
   output wire MemOE,
   output wire MemWR,
   output wire RamAdv,
   output wire RamCS,
   output wire RamClk,
   output wire RamLB,
   output wire RamUB,
   output wire [23:1] MemAdr,
   inout wire [15:0] MemDB

);

//Registers
reg [31:0] state = 0;
reg [7:0] rLed;

reg rMemOE = 1;
reg rMemWR = 1;
reg [15:0] rMemDB;
reg [23:1] rMemAdr;


//Static assignments
assign RamCS = 0;    //chip select is always low (enabled)
assign RamClk = 0;    //clk is disabled in asynchronous mode
assign RamAdv = 0;    //address valid can always be pulled low in
asynchronous mode
assign RamLB = 0;    //lower byte is enabled
assign RamUB = 0;    //upper byte is enabled

//Register assignments
assign MemOE = rMemOE;
assign MemWR = rMemWR;
assign MemDB[15:0] = rMemDB[15:0];
assign MemAdr[23:1] = rMemAdr[23:1];

assign Led[7:0] = rLed[7:0];

always @(posedge clk)
begin
   if(btn[0])                     //btn[0] is reset/write
       state <= 0;
   else if(btn[1])                //btn[1] is read
       state <= 50;
   else if(btn[2])                //btn[2] just toggles Led[7]
       rLed[7] <= ~rLed[7];
   else begin
       case(state)
           0: begin
               rMemAdr <= 23'b0;        //set address to 0
               rMemDB <= 16'h0505;        //write 0x0505 to the data bus
               rMemWR <= 0;            //pull write enable low to write the
data
               state <= 10;
               end
           10: begin
               rMemWR <= 1;            //pull write enable to high again
               end

           50: begin
               rMemDB <= 16'bzzzzzzzzzzzzzzzz;        //set the data bus to
high impedance
               rMemOE <= 0;                        //pull output enable low
to start a read
               state <= 60;
               end
           60: begin
               rLed[3:0] <= MemDB[7:0];            //set the LEDs to show
the data
               state <= 70;
               end
           70: begin
               rMemOE <= 1;                        //pull output enable
high again
               end
       endcase
   end
end


endmodul

2011\10\09@063650 by RussellMc

face picon face
On 8 October 2011 11:28, V G <spam_OUTx.solarwind.xTakeThisOuTspamgmail.com> wrote:
> I would like to share this little slice of happiness with you all. I finally
> got the pSRAM on my Nexys 2 board working in asynchronous mode. Can reliably
> write and read data. Time to get the logic analyzer working.

Congratulations.

I'd say that this merits an [EE] subject tag. It may LOOK like code,
but those arereal bits of hardware that are being decribed.
Anyone agree/disagree



           Russel

2011\10\09@073223 by Michael Watterson

face picon face
On 09/10/2011 11:36, RussellMc wrote:
> Congratulations.
>
> I'd say that this merits an [EE] subject tag. It may LOOK like code,
> but those arereal bits of hardware that are being decribed.
> Anyone agree/disagree
>
>
ethereal hardware is also a good description :-)

Hardware, but not as we know it Jim

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