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'[EE] Verilog modules'
2011\04\30@030140 by V G

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Hey all, I'm trying to make a simple Verilog program to display the hex
value of 4 (binary) switches. The program is organized into two modules.

I've done some reading, but still don't really understand the whole module
business. Anyway, I'm getting an error with my code.

Code: http://pastebin.com/c0jRk1jw

UCF: http://pastebin.com/1DnRY3mB

Error: http://pastebin.com/R6HQm0hr

I'm not sure what's wrong and how to go about fixing this. I know what I
want to do but not really sure how this whole module and parameter passing
thing works, and what a parameter really is in Verilog.

Maybe I should do VHDL first..

2011\04\30@034253 by Oli Glaser

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face
On 30/04/2011 08:01, V G wrote:
> Hey all, I'm trying to make a simple Verilog program to display the hex
> value of 4 (binary) switches. The program is organized into two modules.
>
> I've done some reading, but still don't really understand the whole module
> business. Anyway, I'm getting an error with my code.
>
> Code: http://pastebin.com/c0jRk1jw
>
> UCF: http://pastebin.com/1DnRY3mB
>
> Error: http://pastebin.com/R6HQm0hr
>
> I'm not sure what's wrong and how to go about fixing this. I know what I
> want to do but not really sure how this whole module and parameter passing
> thing works, and what a parameter really is in Verilog.
>
> Maybe I should do VHDL first...

Try changing your output sseg to a reg (so put output reg [7:0] sseg)

2011\04\30@040543 by Oli Glaser

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face
On 30/04/2011 08:01, V G wrote:
> not really sure how this whole module and parameter passing
> thing works, and what a parameter really is in Verilog.

Roughly, a module is simply a reusable chunk of your design (a bit like a class in C++)
So you define your e.g. counter, then instantiate it where you want to - like with your code, in your second module, you declare an instance of the first one.
A parameter is for putting a meaningful name to some variable which can be changed easily (bit like a define in C - you don't have change all the places it's used, just the definition value)
The parameter can be set when instantiating a module. For example you could have:

module hex_to_sseg
#(parameter WIDTH = 8)
    (
    input wire [3:0] hex,
    output reg [WIDTH - 1:0] sseg
    );

....rest of module.... (you would have to change all the "7s" in your module to "WIDTH - 1")

Then when instantiating you could alter the default to create a 16 bit width:
hex_to_sseg sseg_ #(.WIDTH (16)) unit_0(.hex(sw[3:0]), .sseg(seg));

Note - take the C analogies very lightly, the best I could come up with to give a rough idea.
This should all be explained in most starter tutorials or the first chapter of Verilog books.

> Maybe I should do VHDL first...

It will be just as steep a learning curve :-)

2011\04\30@045113 by Michael Watterson

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On 30/04/2011 09:05, Oli Glaser wrote:
> A parameter is for putting a meaningful name to some variable which can
> be changed easily (bit like a define in C - you don't have change all
> the places it's used, just the definition value)

Verilog "modules" are not really modules in sense of VHDL, Especially not in sense of C++ class (more like a C++ template), nor modules in sense of Modula-2.

 They are very like simply a chunk of code in a Macro in Assembler or #define in C. There are no real parameters at all, it's just replacement of aliased name.

Simply pasting a chunk of code from another project and Find/Replace to a name already used is the same thing. There is nowhere to "pass" a parameter.

2011\04\30@081947 by Herbert Graf

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There are two net types in verilog (actually there are more, but to
remain safe in the world of compilable code, stick with the following
two):

wire
reg

The default if you don't specify is wire, in your case you defined your
output bus ssreg to be of type wire.

Wires CANNOT be "written" to by an always block. They can only be driven
by the instantiation of another block, or assigned to by an assign
statement.

In your case, you're driving ssreg in an always block. As such, you have
to declare ssreg as a "reg".

So, in your case, just change your declaration of ssreg to reg.

TTYL



On Sat, 2011-04-30 at 03:01 -0400, V G wrote:
{Quote hidden}

2011\04\30@143304 by V G

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On Sat, Apr 30, 2011 at 3:42 AM, Oli Glaser <spam_OUToli.glaserTakeThisOuTspamtalktalk.net> wrote:

>  Try changing your output sseg to a reg (so put output reg [7:0] sseg)
>
>
It works, but I don't understand why

2011\04\30@143519 by V G

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On Sat, Apr 30, 2011 at 8:19 AM, Herbert Graf <.....hkgrafKILLspamspam@spam@gmail.com> wrote:

> There are two net types in verilog (actually there are more, but to
> remain safe in the world of compilable code, stick with the following
> two):
>
> wire
> reg
>

Yeah, that's the same thing Pong Chu's book says. It's a pretty good book,
but still leaves questions

2011\04\30@144207 by V G

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On Sat, Apr 30, 2011 at 4:05 AM, Oli Glaser <oli.glaserspamKILLspamtalktalk.net> wrote:

{Quote hidden}

Whoops, I should have said "the things in the module brackets". I didn't
actually mean the parameter keyword. I don't really understand the things in
the brackets and why they go in the brackets. I'm trying to picture a module
as an integrated circuit chip and the things in the brackets as pin
definitions as input/output. But I don't understand what a "reg" does and
what it really does inside the chip

2011\04\30@233254 by Herbert Graf

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On Sat, 2011-04-30 at 14:35 -0400, V G wrote:
> On Sat, Apr 30, 2011 at 8:19 AM, Herbert Graf <.....hkgrafKILLspamspam.....gmail.com> wrote:
>
> > There are two net types in verilog (actually there are more, but to
> > remain safe in the world of compilable code, stick with the following
> > two):
> >
> > wire
> > reg
> >
>
> Yeah, that's the same thing Pong Chu's book says. It's a pretty good book,
> but still leaves questions.

Such as?

2011\04\30@234134 by V G

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On Sat, Apr 30, 2011 at 11:32 PM, Herbert Graf <EraseMEhkgrafspam_OUTspamTakeThisOuTgmail.com> wrote:

>  Such as?
>
>
I'll post them when I get to them :


'[EE] Verilog modules'
2011\05\01@003232 by Oli Glaser
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face
On 30/04/2011 19:34, V G wrote:
>   But I don't understand what a "reg" does and
> what it really does inside the chip.

A reg is short for register, e.g. a place to store bits, usually one or more D type flip-flops.
This is the basis of sequential (as opposed to combinational) designs (if your knowledge of digital design is rusty, read a book on it, you need to know this stuff well for FPGAs)
When you compile your design, have a look at the "schematic" in ModelSim (or whatever Xilinx uses)
This is a graphical representation of your design.
You will be able to see what different verilog constructs turn into on the chip. I found this quite useful for getting the hang of visualising what my Verilog is doing, and when to use what construct.
Try and keep it reasonably simple though, otherwise it will be difficult to read easily. You might be surprised what a couple of statements can turn into.
Try things like seeing what an addition of two registers becomes, and compare a case statement to an if else statement. Pong Chu's book goes into things like priority routing and much more, so it should all make sense soon enough if you keep at it.

2011\05\01@015437 by V G

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On Sun, May 1, 2011 at 12:31 AM, Oli Glaser <oli.glaserspamspam_OUTtalktalk.net> wrote:

> When you compile your design, have a look at the "schematic" in ModelSim
> (or whatever Xilinx uses)
> This is a graphical representation of your design.
>

Thanks. I didn't know this was possible. This should help a lot

2011\05\01@020600 by Oli Glaser

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On 01/05/2011 06:54, V G wrote:
> On Sun, May 1, 2011 at 12:31 AM, Oli Glaser<@spam@oli.glaserKILLspamspamtalktalk.net>  wrote:
>
>> When you compile your design, have a look at the "schematic" in ModelSim
>> (or whatever Xilinx uses)
>> This is a graphical representation of your design.
>>
> Thanks. I didn't know this was possible. This should help a lot.

Sorry, I actually meant Synplify (or the Xilinx synthesis tool), not ModelSim.

2011\05\01@020702 by William \Chops\ Westfield

face picon face
On Apr 30, 2011, at 5:19 AM, Herbert Graf wrote:

> Wires CANNOT be "written" to by an always block. They can only be  
> driven
> by the instantiation of another block, or assigned to by an assign
> statement.
>
> In your case, you're driving ssreg in an always block. As such, you  
> have
> to declare ssreg as a "reg".

Interesting.  This decoder is entirely combinatorial; how would it be  written to use plain wires as outputs ?   (without knowing anything at  all about verilog, and only a little about PLDs, that's sort of what I  would have expected "always" block to do...)

BillW

2011\05\01@113446 by Herbert Graf

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On Sun, 2011-05-01 at 05:31 +0100, Oli Glaser wrote:
> On 30/04/2011 19:34, V G wrote:
> >   But I don't understand what a "reg" does and
> > what it really does inside the chip.
>
> A reg is short for register, e.g. a place to store bits, usually one or
> more D type flip-flops.

Actually that is not really true. reg does indeed stand for register,
but it doesn't necessarily mean storage in synthesized hardware. What it
actually means is the simulator running that code needs storage to
implement the logic writing that net.

For example, level sensitive always blocks (vs. edge sensitive) can
often result in logic the doesn't contain any storage in the final
synthesized hardware. Case in point: the following code requires a reg
declaration, but results in zero storage:

reg out;
always @ (in and reset)
begin
       if (reset)
       begin
               out <= 0;
       end
       else
       begin        
               out <= in;
       end
end

Of course, this block COULD have be written as such, and therefore not
requiring a reg definition for out:

assign out = (reset) ? 1'b0 : in;

Which is much closer to the actual logic that would be produced, which
would probably be something like this:

reset -> (NOT) -> (   )
                 (AND) -> out        
in -------------> (   )

Remember, that although it's called a reg in verilog, it doesn't
actually mean a flop.

Another place to be VERY careful with FPGAs is inferred latches. I'll
just say that whatever you do, make sure your code doesn't produce
latches (unless that's exactly the structure you need), you'll avoid
numerous issue down the road. Stick with D flip flops if you can.

TTYL
       

2011\05\01@113543 by Herbert Graf

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On Sun, 2011-05-01 at 07:05 +0100, Oli Glaser wrote:
> On 01/05/2011 06:54, V G wrote:
> > On Sun, May 1, 2011 at 12:31 AM, Oli Glaser<KILLspamoli.glaserKILLspamspamtalktalk.net>  wrote:
> >
> >> When you compile your design, have a look at the "schematic" in ModelSim
> >> (or whatever Xilinx uses)
> >> This is a graphical representation of your design.
> >>
> > Thanks. I didn't know this was possible. This should help a lot.
>
> Sorry, I actually meant Synplify (or the Xilinx synthesis tool), not
> ModelSim.

Synplify is actually a many thousands of dollars tool. Floorplanner is
the tool in ISE that lets you see a schematic view of your routed
design.

TTYL

2011\05\01@114118 by Herbert Graf

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On Sat, 2011-04-30 at 23:06 -0700, William "Chops" Westfield wrote:
> On Apr 30, 2011, at 5:19 AM, Herbert Graf wrote:
>
> > Wires CANNOT be "written" to by an always block. They can only be  
> > driven
> > by the instantiation of another block, or assigned to by an assign
> > statement.
> >
> > In your case, you're driving ssreg in an always block. As such, you  
> > have
> > to declare ssreg as a "reg".
>
> Interesting.  This decoder is entirely combinatorial; how would it be  
> written to use plain wires as outputs ?   (without knowing anything at  
> all about verilog, and only a little about PLDs, that's sort of what I  
> would have expected "always" block to do...)

As I explained in another post, "reg" in verilog does NOT necessarily
mean storage in the synthesized hardware. A properly written case
statement can result in just combinational logic (note that if you don't
properly write it you can infer latches very easily).

If one is "allergic" to the reg statement, a case statement can be
written something like this:

assign ssreg = (control == FIRST) ? first_data :
               (control == SECOND) ? second_data :
               (control == THIRD) ? third_data : fourth_data;

Or something like that, it's personal preference which one prefers.
There is more room for error in this form, but it's much more flexible
then the case type structure.

TTYL

2011\05\01@120659 by Oli Glaser

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face
On 01/05/2011 16:34, Herbert Graf wrote:
> On Sun, 2011-05-01 at 05:31 +0100, Oli Glaser wrote:
>> >  On 30/04/2011 19:34, V G wrote:
>>> >  >     But I don't understand what a "reg" does and
>>> >  >  what it really does inside the chip.
>> >  
>> >  A reg is short for register, e.g. a place to store bits, usually one or
>> >  more D type flip-flops.
> Actually that is not really true. reg does indeed stand for register,
> but it doesn't necessarily mean storage in synthesized hardware. What it
> actually means is the simulator running that code needs storage to
> implement the logic writing that net.

Yes, sorry - what I wrote was misleading. I was trying to keep it as simple as possible by painting a rough picture, but this was probably a bad idea in this case. I did say "usually" though.. :-)




2011\05\01@121039 by Oli Glaser

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On 01/05/2011 16:35, Herbert Graf wrote:
> On Sun, 2011-05-01 at 07:05 +0100, Oli Glaser wrote:
>> On 01/05/2011 06:54, V G wrote:
>>> On Sun, May 1, 2011 at 12:31 AM, Oli Glaser<RemoveMEoli.glaserTakeThisOuTspamtalktalk.net>   wrote:
>>>
>>>> When you compile your design, have a look at the "schematic" in ModelSim
>>>> (or whatever Xilinx uses)
>>>> This is a graphical representation of your design.
>>>>
>>> Thanks. I didn't know this was possible. This should help a lot.
>> Sorry, I actually meant Synplify (or the Xilinx synthesis tool), not
>> ModelSim.
> Synplify is actually a many thousands of dollars tool. Floorplanner is
> the tool in ISE that lets you see a schematic view of your routed
> design.
>
> TTYL

In the free version Actel IDE they use Synplify, and ModelSim for simulation, both launch from the main software (Libero)
 I thought Xilinx might do something similar.

2011\05\01@133442 by Herbert Graf

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On Sun, 2011-05-01 at 17:10 +0100, Oli Glaser wrote:
{Quote hidden}

Wow, really? I didn't know that. Synplify is a very powerful tool, I'm
surprised they include it in any free version of anything! I wonder if
Actel simply decided to use Synplify for all synthesis instead of
developing it's own synthesizer?

AFAIK the webpack for Xilinx only has XST (the Xilinx synthesizer)
available, and for view what's in the FPGA you use either FPGA editor
(the older tool) or Planahead (the new tool that I haven't been able to
play with much yet).

TTYL

2011\05\01@155230 by Oli Glaser

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On 01/05/2011 18:34, Herbert Graf wrote:
>> >  In the free version Actel IDE they use Synplify, and ModelSim for
>> >  simulation, both launch from the main software (Libero)
>> >     I thought Xilinx might do something similar.
> Wow, really? I didn't know that. Synplify is a very powerful tool, I'm
> surprised they include it in any free version of anything! I wonder if
> Actel simply decided to use Synplify for all synthesis instead of
> developing it's own synthesizer?

I think this is probably the case, I have never seen mention of an Actel synthesis tool. I just checked and Synplify Pro AE comes as standard with all versions. Overall I have been very impressed with the Actel parts/tools. I intend to try Xilinx out in the very near future so it will be interesting to see how the tools/parts/prices compare.

2011\05\05@072623 by V G

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Next question: I wrote a simple program to display the value of a
register on 8 LEDs. At the same time, a 4-digit 7-segment display is
multiplexed to show some numbers.

Single module version: http://pastebin.com/mYv7HVfy This one works.
Everything works as expected.

Two module version: http://pastebin.com/BbXkrWBW This one doesn't work
and I don't know how to make it work. I tried to split the
functionality into two modules and now the functionality of the
7-segment multiplexer is lost. What went wrong here?

Also, what exactly are modules in Verilog

2011\05\05@075955 by Herbert Graf

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On Thu, 2011-05-05 at 07:26 -0400, V G wrote:
> Next question: I wrote a simple program to display the value of a
> register on 8 LEDs. At the same time, a 4-digit 7-segment display is
> multiplexed to show some numbers.
>
> Single module version: http://pastebin.com/mYv7HVfy This one works.
> Everything works as expected.
>
> Two module version: http://pastebin.com/BbXkrWBW This one doesn't work
> and I don't know how to make it work. I tried to split the
> functionality into two modules and now the functionality of the
> 7-segment multiplexer is lost. What went wrong here?
>
> Also, what exactly are modules in Verilog?

You're main isn't calling your submodule, so it's being eliminated.

Like in C there is only one "main". In Verilog the "root" module is the
top of the tree.
In your case, change main as follows:

module main(            input wire clk,
       output reg [7:0] Led,
       output [3:0] an,
       output [6:0] seg
       );
               reg [32:0] count;
                       always @ (posedge clk) begin
               count = count + 1;
               Led[7:0] = count[27:20];                        end
               led_mux unit0(.clk(clk), .an(an), .seg(seg) );
       endmodule

Remember, just because something is labeled "output" or "input" it
doesn't mean it's actually leaving the chip. Those declarations only
have relevance to that module. In your case, clk is an input to led_mux,
and an and seg are outputs to led_mux.

A "module" is a chunk of logic, similar to how a function in C is a
chunk of code.

TTYL

2011\05\05@080903 by V G

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On Thu, May 5, 2011 at 7:59 AM, Herbert Graf <TakeThisOuThkgrafEraseMEspamspam_OUTgmail.com> wrote:
{Quote hidden}

Thanks. That works, but lets say the main module gets complicated and
has a million inputs and outputs (in the parenthesis). I wanted to
declare all those only in the led_mux  module and not in the main
module up top. How can I do that? Why is it necessary to add the an
and seg outputs to the main module? Why can't the led_mux module
handle those on its own?

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