Post by thread:[EE] TQFP lead pitch variations

Good day to all. Got a dumb question here: we just got back some proto boards done with the PIC 18F67J60. Went to populate the boards - whoops! Got a problem here. The TQFP-64 package that was in the CAD library doesn't match the PIC received from Digikey. Turns out that the TQFP package in the CAD library has a 0.80mm lead pitch whereas the PIC has a 0.50mm lead pitch. Like I said: Whoops! So - my co-worker is busy making a new footprint to match the actual chip. But that has me wondering: how do people define these footprints? I did some minor searching via Google and find that we aren't the only people perplexed by this - Microchip apparently offers TQFP packages with 4 different lead pitches: 0.40mm, 0.50mm, 0.65mm, 0.80mm. I'm looking for suggestions as to how to name these footprints - I'd like to follow whatever convention has been developed rather than come up with something totally different from what everyone else uses. This particular incident wasn't my mistake but it easily could have been - I'm sorta used to a package name (eg SOIC) having a specified lead pitch and I might have decided to skip my usual "check twice" policy. As it was, I did have a good look at the board layout before it was sent out and it *NEVER* occurred to me that the PIC footprint might be wrong. dwayne -- Dwayne Reid <spam_OUTdwaynerTakeThisOuTplanet.eon.net> Trinity Electronics Systems Ltd Edmonton, AB, CANADA (780) 489-3199 voice (780) 487-6397 fax http://www.trinity-electronics.com Custom Electronics Design and Manufacturing

On Thu, 2011-07-14 at 19:00 -0600, Dwayne Reid wrote: > This particular incident wasn't my mistake but it easily could have > been - I'm sorta used to a package name (eg SOIC) having a specified > lead pitch and I might have decided to skip my usual "check twice" > policy. As it was, I did have a good look at the board layout before > it was sent out and it *NEVER* occurred to me that the PIC footprint > might be wrong. FWIW I sometimes go so far as to make scale models of my board and "unfamiliar" parts to ensure parts are what I expect them to be... that said, the days of assuming pitch are long over. A friend of mine a few years ago made a board that we ALL checked. Only after it came back did we realize that the JTAG header on the board was 2.54mm pitch, and the JTAG programming cable was 2mm pitch... we've had to use the flying lead adapter ever since. TTYL

Dwayne, Not a dumb question at all. Not only can the lead pitch change, so can the chip body size. I found this out when I had to go to surface mount and a lot of footprints seemed to be wrong. I found this standard IPC-7351 at landpatterns.ipc.org/IPC-7351BNamingConvention.pdf Names end up being quite long though. Maybe a local variation might have to be adopted. Mentor Grpahics also have a viewer and wizard for calculating land patterns.. In the wizard, you can enter the dimensions and tolerances of a given part, and it will give you a pattern and dimensions, including courtyards, masks, overlays etc. It also allows you to choose between several different density spacings (ie how densley packed your board has to be). Tom Hausherr seems to be rather knowledgeable in this area. A google search should find him. Cheers, David {Original Message removed}

On 15/07/2011 02:00, Dwayne Reid wrote: > But that has me wondering: how do people define these footprints? > I have wondered about this too :-) I name the footprints with the pitch and manufacturer, and if they have their own naming system I usually use that (whatever they call the footprint in their datasheet), or maybe the JEDEC code if they refer to that (usually you get a note saying it conforms with JEDEC code xxxx) If there is no "special" name then I use something like e.g. in microchip footprint library: TQFP100_12x12_P0.4 It's a pain, I wish there was a bit more effort to maybe standardise the naming or manufacturers provide a reference document with recommended footprints for all their parts (some are better than others for this kind of thing) Often I find you get a drawing of the chip dimensions on the manufacturers website but no recommended footprint drawing. When this is the case I type the code (common name, JEDEC name, etc) into Google and use the best I can find, or design from the chip dimensions. I think there are a few tools that do this automatically for you, you just type the dimensions in and it calculates the standard footprint (e.g. Altium and DesignSpark have this built in - I bet there's probably a free web based one somewhere too) I keep a folder with these footprint datasheets and link them to the footprints in Kicad so I can check the dimensions easily. I used to have a standard SMD footprint library (e.g. SOIC8, SOIC20, TQFP64, etc) for all parts, but I learnt that different manufacturers seem to have different ideas about the same names, so now I make a separate library for each manufacturers footprints. It's a bit more work, and I probably have quite a few duplicate footprints with different names, but at least I know I can trust them.

Like Herbert, I almost always print out a 1:1 scale artwork of the component side(s) of the board and physically lay unfamiliar parts on the paper and view the alignment under magnification. Most CAD software can do this (produce exact scale output) natively but even if it cannot, you can always do it from the Gerber files. I find that most printers are fairly accurate. They may be off by, say, 1 mm over the length of an 8 inch long board, which is negligible over the scale of a single surface mount IC. Sean On Thu, Jul 14, 2011 at 9:17 PM, Herbert Graf <.....hkgrafKILLspam@spam@gmail.com> wrote: {Quote hidden}> On Thu, 2011-07-14 at 19:00 -0600, Dwayne Reid wrote: >> This particular incident wasn't my mistake but it easily could have >> been - I'm sorta used to a package name (eg SOIC) having a specified >> lead pitch and I might have decided to skip my usual "check twice" >> policy. As it was, I did have a good look at the board layout before >> it was sent out and it *NEVER* occurred to me that the PIC footprint >> might be wrong. > > FWIW I sometimes go so far as to make scale models of my board and > "unfamiliar" parts to ensure parts are what I expect them to be... > > that said, the days of assuming pitch are long over. A friend of mine a > few years ago made a board that we ALL checked. Only after it came back > did we realize that the JTAG header on the board was 2.54mm pitch, and > the JTAG programming cable was 2mm pitch... we've had to use the flying > lead adapter ever since. > > TTYL > >

Microchip has a full document on all the packages they use: <www.microchip.com/stellent/groups/techpub_sg/documents/packagingspec/en012702.pdf> This is from the Packaging specifications page off of the page at http://www.microchip.com. Matt Bennett Just outside of Austin, TX 30.51,-97.91 The views I express are my own, not that of my employer, a large multinational corporation that you are familiar with. On Thu, July 14, 2011 11:11 pm, Sean Breheny wrote: {Quote hidden}> Like Herbert, I almost always print out a 1:1 scale artwork of the > component side(s) of the board and physically lay unfamiliar parts on > the paper and view the alignment under magnification. Most CAD > software can do this (produce exact scale output) natively but even if > it cannot, you can always do it from the Gerber files. I find that > most printers are fairly accurate. They may be off by, say, 1 mm over > the length of an 8 inch long board, which is negligible over the scale > of a single surface mount IC. > > Sean > > > On Thu, Jul 14, 2011 at 9:17 PM, Herbert Graf <hkgrafKILLspamgmail.com> wrote: >> On Thu, 2011-07-14 at 19:00 -0600, Dwayne Reid wrote: >>> This particular incident wasn't my mistake but it easily could have >>> been - I'm sorta used to a package name (eg SOIC) having a specified >>> lead pitch and I might have decided to skip my usual "check twice" >>> policy. As it was, I did have a good look at the board layout before >>> it was sent out and it *NEVER* occurred to me that the PIC footprint >>> might be wrong. >> >> FWIW I sometimes go so far as to make scale models of my board and >> "unfamiliar" parts to ensure parts are what I expect them to be... >> >> that said, the days of assuming pitch are long over. A friend of mine a >> few years ago made a board that we ALL checked. Only after it came back >> did we realize that the JTAG header on the board was 2.54mm pitch, and >> the JTAG programming cable was 2mm pitch... we've had to use the flying >> lead adapter ever since. >> >> TTYL >> >> -

On 15/07/2011 02:17, Herbert Graf wrote: > On Thu, 2011-07-14 at 19:00 -0600, Dwayne Reid wrote: >> > This particular incident wasn't my mistake but it easily could have >> > been - I'm sorta used to a package name (eg SOIC) having a specified >> > lead pitch and I might have decided to skip my usual "check twice" >> > policy. As it was, I did have a good look at the board layout before >> > it was sent out and it*NEVER* occurred to me that the PIC footprint >> > might be wrong. > FWIW I sometimes go so far as to make scale models of my board and > "unfamiliar" parts to ensure parts are what I expect them to be... > > that said, the days of assuming pitch are long over. A friend of mine a > few years ago made a board that we ALL checked. Only after it came back > did we realize that the JTAG header on the board was 2.54mm pitch, and > the JTAG programming cable was 2mm pitch... we've had to use the flying > lead adapter ever since. I like to print it on paper actual size and set all the parts on the paper. Even if pads are correct a Keep-out or clearance could be wrong. I know some packages do 3D models. But that's not a check. The real components may be different to 3D library

> I'm looking for suggestions as to how to name these footprints - I'd > like to follow whatever convention has been developed rather than > come up with something totally different from what everyone else uses. > > This particular incident wasn't my mistake but it easily could have > been - I'm sorta used to a package name (eg SOIC) having a specified > lead pitch and I might have decided to skip my usual "check twice" > policy. As it was, I did have a good look at the board layout before > it was sent out and it *NEVER* occurred to me that the PIC footprint > might be wrong. Name them with the JEDEC footprint name - the problem here is that the manufacturers often never reference the JEDEC footprint names in their documents, but sometimes you will see a 'corresponds to JEDEC xxxx' footnote on their package drawings. e.g. your SOIC is an MS-012AA for an SO-8, through to MS-012AC for an SO-16, all 0.3" wide, MS-013xx for the 0.4" wide family (even though they also are known as SO-24 etc), and so on. Once you get used to the JEDEC names they do work a lot better, least we have found that around here. -- Scanned by iCritical.

> It's a pain, I wish there was a bit more effort to maybe standardise the > naming or manufacturers provide a reference document with recommended > footprints for all their parts (some are better than others for this > kind of thing) Often I find you get a drawing of the chip dimensions on > the manufacturers website but no recommended footprint drawing. I just wish that manufacturers would specifically say that the part 'conforms to JEDEC xxxx' or the equivalent European standard, I don't care which they reference, so long as it is one of them. -- Scanned by iCritical.

> -----Original Message----- > From: .....piclist-bouncesKILLspam.....MIT.EDU On Behalf Of EraseMEalan.b.pearcespam_OUTTakeThisOuTstfc.ac.uk > Sent: Friday, July 15, 2011 4:20 AM > > Name them with the JEDEC footprint name - the problem here is > that the manufacturers often never reference the JEDEC > footprint names in their documents, but sometimes you will > see a 'corresponds to JEDEC xxxx' footnote on their package drawings. > > e.g. your SOIC is an MS-012AA for an SO-8, through to > MS-012AC for an SO-16, all 0.3" wide, MS-013xx for the 0.4" > wide family (even though they also are known as SO-24 etc), and so on. > > Once you get used to the JEDEC names they do work a lot > better, least we have found that around here. I second the use of the JEDEC standard names, I had my employer switch to them a few years ago. IIRC, the standards are free to download from <http://www.jedec.org/> (free site registration required). For are some more JEDEC names for specific Microchip TQFPs: Microchip 64 lead, 14x14x1, 0.80 pitch = MSO-26AEB Microchip 80 lead, 14x14x1, 0.65 pitch = MSO-26AEC Microchip 64 lead, 10x10x1, 0.50 pitch = MSO-26ACD Microchip 80 lead, 12x12x1, 0.50 pitch = MSO-26ADD Paul Hutch

> -----Original Message----- > From: @spam@piclist-bouncesKILLspammit.edu On Behalf Of William "Chops" Westfield > Sent: Saturday, July 23, 2011 3:20 AM > > On Jul 15, 2011, at 1:20 AM, KILLspamalan.b.pearceKILLspamstfc.ac.uk wrote: > > > your SOIC is an MS-012AA for an SO-8, through to MS-012AC for an > > SO-16 ... > > > > Once you get used to the JEDEC names they do work a lot better > > Is there any logic to the JEDEC names? Those examples seem pretty > random! There is at least some logic to the JEDEC package naming however, with the impossibility of predicting future packaging variations, I'm not certain they have been able to keep the logic fully intact over the last 50+ years. Here's the basics, The first two letters followed by a dash and a number give the basic package outline. Examples: MS-001 = Dual inline plastic family, 0.300 inch row spacing MS-012 = Plastic small outline family, 1.27mm pitch, 3.90mm body width MS-013 = Plastic small outline family, 1.27mm pitch, 7.50mm body width MO-187 = Plastic, low/thin/very thin, small outline package, 0.65 and 0.50 pitch TO-92 = I hope everyone on the list knows what this one is :-) The letters following the base number give the variations in the package. Examples: MS-012AA = 8 pin, 4.90mm length MS-012AB = 14 pin, 8.65mm length MS-012AC = 16 pin, 9.90mm length The variation letters are logically assigned within each basic package type however an "A" in one package might not be the same variation as an "A" for another basic package. Paul Hutch > > BillW

> > your SOIC is an MS-012AA for an SO-8, through to MS-012AC for an > > SO-16 ... > > > > Once you get used to the JEDEC names they do work a lot better > > Is there any logic to the JEDEC names? Those examples seem pretty > random! Yes there is, the first part (in this case MS-012) specifies the package width and pin spacing (in this case it is a 0.3" package with 0.05" pin spacing), and the second part specifies the number of pins, here AA is 8 pins, AB is 14 pins, AC is 16 pins. MS-013 is the 0.4" package, and IIRC AA is 20 pins, AB is 24 pins, AC is 28 pins. I think the situation does change once you go to the square packages, but I haven't had much to do with those. -- Scanned by iCritical.

> > > your SOIC is an MS-012AA for an SO-8, through to MS-012AC for an > > > SO-16 ... > > > > > > Once you get used to the JEDEC names they do work a lot better > > > > Is there any logic to the JEDEC names? Those examples seem pretty > > random! > > Yes there is, the first part (in this case MS-012) specifies the package width and > pin spacing (in this case it is a 0.3" package with 0.05" pin spacing), and the > second part specifies the number of pins, here AA is 8 pins, AB is 14 pins, AC is 16 > pins. > > MS-013 is the 0.4" package, and IIRC AA is 20 pins, AB is 24 pins, AC is 28 pins. > > I think the situation does change once you go to the square packages, but I haven't > had much to do with those. In the process of doing something else, I had occasion to look for the Jedec page where these are defined. http://www.jedec.org/standards-documents/technology-focus-areas/registered-outlines-jep95 (although I think someone else also posted a link to the base Jedec site). Note the "Microelectronic Standards" section which is all the outlines classed as MS-xxx. The TO, DO etc outlines are in spate sections. And from the 'table of contents' in the MS section, my descriptions of the widths above is inaccurate, as the standard works to the body width, not the overall width (which is what I was giving above, but describing it as 'package width'). To download the actual standards you do need a login. -- Scanned by iCritical.