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I want to try out SystemVerilog. However, it seems that Xilinx XST doesn't
support it yet (as far as I know). Altera's Quartus seems to support it.
Also, Synplify supports it. Can I somehow use the Quartus synthesis tool in
On Thu, 2011-10-06 at 18:09 -0400, V G wrote:
> I want to try out SystemVerilog.
I wouldn't bother, yet.
The majority of the ASIC industry is using VHDL and Verilog.
In the FPGA world pretty much NOBODY is using SV, I know, I've looked.
The good news is since SV is a superset of Verilog, learning Verilog
very well gets you quite close to SV.
Since the most useful of features in SV tend more toward the simulation
environment I'd stick there for your SV adventures, when you know
Verilog REALLY well.
> However, it seems that Xilinx XST doesn't
> support it yet (as far as I know). Altera's Quartus seems to support it.
> Also, Synplify supports it. Can I somehow use the Quartus synthesis tool in
> Xilinx ISE?
No. The tools synthesize to their part's respective primitives.
Theoretically you could create an RTL translation layer that maps Altera
primitives to Xilinx primitives, the effort is NOT worth it IMHO.
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