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'[EE] Stability of linear regulators'
2006\09\10@224441 by

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Hi all,

As you all know, linear regulators essentially consisting of an
op-amp, voltage reference, and pass transistor are very common. One
drawback is that they cannot sink current, only source it. The first
time I tried to design such a regulator, I had an awful time trying to
get it to stop oscillating. I eventually discovered that this was
because of the nonlinear behavior of the pass transistor at low
currents (essentially because if the capacitance on the output got
charged to even slightly too high a voltage and there was no load on
the output, the op-amp's output would swing all the way to the
negative rail untl the cap drifted down a bit in voltage).

I've attached a small PDF of a circuit to illustrate this. An LTSpice
simulation of this circuit shows it to be unstable when the current
being drawn from the output jumps from 10mA to 1A.

One way to mitigate this is to put a resistor in the feedback path and
a capacitor directly from the op-amp output to its inverting input,
thus slowing down the response. However, no matter how large I make
this compensation capacitor, large enough output capacitor values will
eventually cause instability. The same is true if I put a resistor on
the output to draw a minimum load (to reduce the nonlinearity of the
pass transistor at low currents).

I've often heard of regulators being unstable with too little
capacitance on the output, but I've never heard anyone complain of
what happens when you have too much capacitance on the output.

Is there something I'm missing here?

Thanks,

Sean

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try to look for error amp in an op-amp book. It should
have a diagram on how it should be used.

John

--- Sean Breheny <shb7cornell.edu> wrote:

{Quote hidden}

> > --

{Quote hidden}

That's not a very realistic circuit as you have included no compensation which would inevitably be present in a linear regulator design to prevent exactly this kind of behaviour.  The phase shift through the transiator and cap will undoubtedly be high enough to sustain oscillation at some frequency.  It looks like you are using Switcher Cad, so you can find out for yourself where the problem area lies.  Open the loop (i.e. remove feedback), bias the circuit to a suitable working point and run a Bode plot, observing the loop gain and phase.  To prevent oscillation the phase should be well away from 180 degrees at 0dB loop gain.  If not you need to add compensation to acheive this.  Some useful op-amp compensation can be found at http://www.intersil.com/data/an/an9415.pdf#search=%22lead%20lag%20compensation%23%22

Note that many LDO's are sensitive to low ESR capacitors on their output (such as ceramic caps), which can cause oscillation.

Regards

Mike

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1000uF on a low output impedance emiter circuit ?
The output capacitor should be low, 10uF up to 100uF..
You must have resistors on both OA inputs.

Vasile

On 9/11/06, Sean Breheny <shb7cornell.edu> wrote:
{Quote hidden}

> -

2006\09\19@181045 by
Thanks to everyone who replied to this. I'm still playing with the
circuit. The problem I'm having is this:

I'm trying to design a linear bench power supply. Given that the bench
supply can be connected to any circuit (which may have an arbitrarily
high capacitve load), I need it to be stable. In addition, I'd like it
to settle within 100 microseconds after a disturbance (either line or

It seems that it is not possible to achieve stability with very large
capacitive loads AND guarantee fast settling times, even when the
capacitve load is less. (This is the way it seems to me after playing
with it, I have no proof of this yet). This is because you essentially
have to either design for a particular capacitve load (where you get
fast response but there is then some max capacitance you can tolerate
and still be stable) or you have to let the output capacitance
dominate the response (dominant pole compensation), in which case you
are essentially designing for the worst case (highest) output
capacitance and response will be slow.

I guess this isn't too surprising a result, but I was just wondering
why I'd never seen this discussed before. I've seen linear regulators
with a MINIMUM output capacitance spec, but never a maximum output
capacitance spec.

Sean

On 9/11/06, Vasile Surducan <piclist9gmail.com> wrote:
{Quote hidden}

Sean,

I found that LM 1117 works well for me. I had no
problems so far on my side with the regulator. The
list did mention some other regulator but I can't
remember the name. Try to check the archive for LM
1117 and you would see some pretty interesting
suggestion.

John

--- Sean Breheny <shb7cornell.edu> wrote:

{Quote hidden}

>
Thank you, John, but I'm doing this more to learn about the design of
regulators than just to get a power supply.

Sean

On 9/19/06, John Chung <kravnusyahoo.com> wrote:
{Quote hidden}

>
> I'm trying to design a linear bench power supply. Given that the bench
> supply can be connected to any circuit (which may have an arbitrarily
> high capacitve load), I need it to be stable. In addition, I'd like it
> to settle within 100 microseconds after a disturbance (either line or
you aren't going to bring up a huge capacitive load from zero instantly to a
high voltage as you will hit the regulators current limits.

> It seems that it is not possible to achieve stability with very large
> capacitive loads AND guarantee fast settling times, even when the
> capacitve load is less. (This is the way it seems to me after playing
> with it, I have no proof of this yet). This is because you essentially
> have to either design for a particular capacitve load (where you get
> fast response but there is then some max capacitance you can tolerate
> and still be stable) or you have to let the output capacitance
> dominate the response (dominant pole compensation), in which case you
> are essentially designing for the worst case (highest) output
> capacitance and response will be slow.
remember (despite the fact that non switchers are reffered to as linear
power supplies) regulators are by definition nonlinear devices, the output
voltage basically cannot rise over what the regulator is set at because if
it is taken above that voltage the conditions that allow current to flow
rapidly collapse (e.g. if an emmiter follower is the output stage of your
design the base-emmitter junction enters into reverse bias and the
transistor turns off).

generally significant disturbance to the output voltage shouldn't happen in
the first place, thats what the capacitors are for! so your only issue is
rise time on powerup and this is mainly reduced by designing the PSU for
high current output.

i just can't see how you are managing to get instability out of a simple PSU
design unless you are working with seriously broken models, maybe post some
links to the circuits you are considering so we can see for ourselves..

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In that case use this and run the schematic using
LTSpice. Play around with the voltage.

John

component better. From the BJT to zener. It is like
reading what they like and don like. Each component
behave differently under different circumstance. OPAMP