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'[EE] Re: How is this transceiver speed possible?'
On Sat, 2011-10-29 at 11:20 -0400, V G wrote:
> Hi Herbert,
> Just a quick question about the Spartan FPGAs. The Spartan 3E FPGAs
> can do up to 666Mbit/s via LVDS and you said that was possible by
> sampling on both clock edges. The Spartan 6 FPGAs have either
> 1080Mbit/s (LX series) or 3.125Gbit/s (GTP tranceivers on the LXT) IO.
> I think the Spartan 6 has up to 540MHz operation and can signal at
> 1080Mbit/s. But what about the LXT? How can it signal at 3.125Gbit/s?
> Is it some sort of parallel in, serial out transceiver?
> You have to start looking at more then just the raw speeds of the IOs
and look more closely at what those speeds refer to.
You're right, a "normal" IO is in no way capable of switching at
3.125GHz using fabric. What that number refers to is the RocketIO
transceiver in those parts.
To support high speed serial protocols like PCIE, SATA, Ethernet, etc,
FPGAs for years have had high speed serial-parallel transceivers. Xilinx
called theirs RocketIO (I think they are deprecating that name, I hear
it less and less in conversation). There have been several generations,
the V6 parts have some IOs that support serial speeds of I think
Again, how the fabric deals with such fantastic speeds is through
parallelism. If you look up the GTP transceiver you'll see that it's
high speed side is single bit differential, while it's low side speed is
likely 10 or 20 bits wide (I'm guessing, it could be other widths
depending how you configure the block in coregen).
On Sat, Oct 29, 2011 at 12:40 PM, Herbert Graf <gmail.com> wrote: hkgraf
> You're right, a "normal" IO is in no way capable of switching at
> 3.125GHz using fabric.
Which makes me wonder how desktop CPUs switch at over 3GHz internally, and
2GHz(1GHz?) on the front side bus (which is IO).
Thank you, that's exactly what I was wondering
I always used to wonder this, too, but I think that the answer is that
internal interconnects can have FAR less capacitance than ones that
have to make it out to the outside of the chip. The primary limitation
on digital gate switching time is how fast the FETs can charge and
discharge the parasitic capacitance which is connected to their
output. A 3 mm long bond wire connected to a bond pad on one side and
the output pin on the other has much more capacitance than a 10
micron-long trace within the die.
On Sat, Oct 29, 2011 at 1:07 PM, V G <gmail.com> wrote: x.solarwind.x
|On Sat, 2011-10-29 at 13:07 -0400, V G wrote:
> On Sat, Oct 29, 2011 at 12:40 PM, Herbert Graf <gmail.com> hkgraf
> You're right, a "normal" IO is in no way capable of switching
> 3.125GHz using fabric.
> Which makes me wonder how desktop CPUs switch at over 3GHz internally,
> and 2GHz(1GHz?) on the front side bus (which is IO).
Same as how the hi speed transceivers in FPGAs do it: through VERY
CPUs are massively pipelined beasts, with tons of custom logic (vs.
things like GPUs which tend to use the fab libraries for pretty much all
logic). Since everything is set in stone when the CPU is designed paths
can be optimized as much as possible for speed.
In an FPGA the tradoff of near infinite logic flexibility is relatively
large distances between chunks of logic. That is why the equivalent
amount of logic in an FPGA uses MUCH less die area in an ASIC. You can
design a transistor to switch really really fast, but if the next
transistor is a fair distance away you'll only be able to run that logic
at some much lower speed.
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