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'[EE] Making sure an NE555 gets reset at startup'
2008\01\01@172451 by Rikard Bosnjakovic

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part 1 1314 bytes content-type:text/plain; charset=ISO-8859-1 (decoded 7bit)

I've hooked up an NE555 in monostable mode which is triggered by a
PIC. While functioning perfectly, there is one small annoyance that
beats me of why it happens and how I can prevent it.

The reset-pin on the 555 is hooked to a 10k pull-up and the
trigger-pin is connected directly to the PIC (no caps or anything
between). The weird thing is this: When powering up, the 555 is
triggered, despite the fact that except for the INTOSC-calibration the
first thing I'm doing in the PIC is to set TRIS to output and set the
ports to '1'. Why this is weird is because the 555 is supposed to trig
on negative flanks according to the datasheet, and the PIC-pins go
from either 1->1 or 0->1 (depening on their values on startup) but
never from 1->0->1.

I'm attaching the small code if anyone wants to peek, but I doubt the
error is in there.

Anyway, a hardware solution for this problem would be to let the
reset-pin on the 555 stay low (i.e. ignoring any triggers) for about a
second after starting up, but I'm not sure how to implement this.
Sure, I can make it non-simple by adding another 555, or a bunch of
other IC's, but I'm pretty sure this delay can be achieved by using
RC-logic. Although I have yet no clue how to do it.

--
- Rikard - http://bos.hack.org/cv/


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part 3 35 bytes content-type:text/plain; charset="us-ascii"
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2008\01\01@180640 by Spehro Pefhany

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At 05:24 PM 1/1/2008, you wrote:
{Quote hidden}

You should set the relevant port bit to '1' *before* you write to
TRIS. The power-up state of the port bits is undefined. If the value
at power-up happens to be 0, you're generating a nice clean trigger pulse.

If absence of false operation at power-up is important, I would also suggest
using external /MCLR, an external reset circuit (tied to both /RESET and
/MCLR), and a pullup resistor on the trigger output so it gets pulled up
towards Vdd during the power-up.

Or dump the 555 entirely and do the timing inside the program.

>Best regards,

Spehro Pefhany --"it's the network..."            "The Journey is the reward"
spam_OUTspeffTakeThisOuTspaminterlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com



2008\01\01@190428 by Jinx

face picon face
> Anyway, a hardware solution for this problem would be to let the
> reset-pin on the 555 stay low (i.e. ignoring any triggers) for about
> a second after starting up

Keep the 10k from Reset to Vcc, add 10n from Reset to 0V. You
need the 555 to power-up with Reset lagging behind Vcc. Just like
a PIC does with external RC

2008\01\01@191151 by Rikard Bosnjakovic

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On 02/01/2008, Spehro Pefhany <.....speffKILLspamspam@spam@interlog.com> wrote:

> pullup resistor on the trigger output so it gets pulled up
> towards Vdd during the power-up.

Thanks, this solved the entire problem.

Now I'm going to try to get a grip of what's happening in the pullup
when the output is 0.


--
- Rikard - http://bos.hack.org/cv/

2008\01\01@192040 by Clint Sharp

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In message <7.0.0.16.2.20080101175644.05f2d710spamKILLspaminterlog.com>, Spehro
Pefhany <.....speffKILLspamspam.....interlog.com> writes
>Or dump the 555 entirely and do the timing inside the program.
Or if the OP absolutely has to have an extra 8 pin chip use one of the
10F series.
>
>>Best regards,
>
>Spehro Pefhany --"it's the network..."            "The Journey is the reward"
>EraseMEspeffspam_OUTspamTakeThisOuTinterlog.com             Info for manufacturers: http://www.trexon.com
>Embedded software/hardware/analog  Info for designers:  http://www.speff.com
>
>
>

--
Clint Sharp

2008\01\01@193130 by Jinx

face picon face
> and a pullup resistor on the trigger so it gets pulled up
> towards Vdd during the power-up.

I meant to mention that in the other post. Floating or low will
trigger the 555 even if Reset has RC


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