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'[EE] FPGA look up table'
2011\05\03@191625 by V G

picon face
Hey all,

I'm now reading into the inner workings of FPGAs to better understand how
they work. The look up table seems to be the most confusing part for me.

1. I don't really understand what it IS or what it DOES. Can anyone please
explain? I know a logic cell in a Spartan 3e FPGA, for example, contains a 3
input LUT and a DFF, but I don't understand what the LUT does or what it's
made of (gate wise).

2. Does the LUT itself provide the logic functionality? As in AND, OR, XOR,
NOT, whatever gates? If so, where are the inputs to the gates, and what are
the LUT inputs for?

3. What kind of "function" can LUTs provide?

I've searched around but can't find many answers on the Internet

2011\05\03@194141 by William \Chops\ Westfield

face picon face

On May 3, 2011, at 4:16 PM, V G wrote:

> 2. Does the LUT itself provide the logic functionality? As in AND,  
> OR, XOR,
> NOT, whatever gates? If so, where are the inputs to the gates, and  
> what are
> the LUT inputs for?
>
> 3. What kind of "function" can LUTs provide?

a LUT provides a logical output capable of computing ANY logical  equation based on its inputs.
Given three inputs, there are only 8 possible outputs.  I think of a  LUT as an array of bits, addressed by the inputs.  You get to specify  the array contents (and thus the logic function) as part of the device  programming.  On many devices, the LUT may actually be implemented as  a RAM array of bits, but I don't think that that is actually required.  Other implementations are possible.

So if you wanted to implement an AND function, your 3-bit LUT would  have zeros in all the table locations except the one corresponding to  1 1 1 inputs.

BillW

2011\05\03@201431 by V G

picon face
On Tue, May 3, 2011 at 7:41 PM, William "Chops" Westfield <spam_OUTwestfwTakeThisOuTspammac.com>wrote:

>  a LUT provides a logical output capable of computing ANY logical
> equation based on its inputs.
> Given three inputs, there are only 8 possible outputs.  I think of a
> LUT as an array of bits, addressed by the inputs.  You get to specify
> the array contents (and thus the logic function) as part of the device
> programming.  On many devices, the LUT may actually be implemented as
> a RAM array of bits, but I don't think that that is actually required.
> Other implementations are possible.
>

So do the three inputs of the LUT select its function, or provide the data
to be computed?


> So if you wanted to implement an AND function, your 3-bit LUT would
> have zeros in all the table locations except the one corresponding to
> 1 1 1 inputs.
>

Oh! So one would select the LUT functionality based on known inputs and
outputs, as in AND(1, 1) -> 1

2011\05\03@212240 by Herbert Graf

picon face
On Tue, 2011-05-03 at 19:16 -0400, V G wrote:
> Hey all,
>
> I'm now reading into the inner workings of FPGAs to better understand how
> they work. The look up table seems to be the most confusing part for me.
>
> 1. I don't really understand what it IS or what it DOES. Can anyone please
> explain? I know a logic cell in a Spartan 3e FPGA, for example, contains a 3
> input LUT and a DFF, but I don't understand what the LUT does or what it's
> made of (gate wise).

Physically a LUT is actually composed of two things: a MUX and an SRAM.

The select pins of the MUX are the inputs to the LUT, the inputs to the
MUX are connected to the dedicated SRAM.

a 3 input LUT contains a MUX with 3 select lines and 8 input lines
connected to an 8 bit SRAM.

> 2. Does the LUT itself provide the logic functionality? As in AND, OR, XOR,
> NOT, whatever gates? If so, where are the inputs to the gates, and what are
> the LUT inputs for?
>
> 3. What kind of "function" can LUTs provide?

A 3 input LUT can perform ANY combinational function that has 3 inputs
and 1 output. That's what makes LUTS so powerful. A 3 input LUT can
easily replace several "standard" logic cells. One of the roles of the
synthesizer is to combine combinational logic in a way as to cram as
much functionality into each and every LUT.

When you "program" an FPGA, one of the things you are doing is loading
the contents of every SRAM connected to a LUT.

TTYL

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