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'[EE] FPGA block RAM vs distributed RAM vs register'
2011\10\09@154635 by V G

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My FPGA is the Xilinx Spartan 3E 500K gates.

1. What is the difference between block RAM and distributed RAM? I know
registers can be implemented as flip flops, but are the implemented in logic
or in the RAM? What's going on here exactly?

2. When I look at the Spartan 3 data sheet, it sizes the different parts in
number of gates and gives an "equivalent number of logic cells". When I look
at the Spartan 6 data sheet, it sizes the parts in logic cells and gives
"equivalent number of gates". What's going on here? Are both the series
structurally similar? Don't both have logic cells and slices and so on

2011\10\09@194216 by Christopher Head

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On Sun, 9 Oct 2011 15:46:20 -0400
V G <spam_OUTx.solarwind.xTakeThisOuTspamgmail.com> wrote:

> My FPGA is the Xilinx Spartan 3E 500K gates.
>
> 1. What is the difference between block RAM and distributed RAM? I
> know registers can be implemented as flip flops, but are the
> implemented in logic or in the RAM? What's going on here exactly?

Block RAM is a large chunk of RAM built in a single place on the chip.
Distributed RAM is RAM implemented by reusing the LUT (*NOT* the
flip-flop!) in a logic block as a small number of RAM bits (hence it's
"distributed" throughout the chip, in the SLICEMs). Neither of these
are the same as the logic block's flip-flop, which only stores one bit
but provides that storage in addition to using the LUT for computation.

As an aside, in addition to being used as RAM or a computational LUT,
the LUTs in SLICEMs can also be used as shift registers. This is all
set up at bitstream load time; the purpose of a particular LUT can't be
changed during execution. Also, LUTs that are in SLICELs, rather than
SLICEMs, can't be used as distributed RAM nor as shift registers.

The gory details are all in chapters four through seven of the Spartan
3 user guide. Also, you may get more answers on the USENET group
comp.arch.fpga than here, this being the PICLIST and all. There are
some real experts there, including people who work at Xilinx and Altera.

> 2. When I look at the Spartan 3 data sheet, it sizes the different
> parts in number of gates and gives an "equivalent number of logic
> cells". When I look at the Spartan 6 data sheet, it sizes the parts
> in logic cells and gives "equivalent number of gates". What's going
> on here? Are both the series structurally similar? Don't both have
> logic cells and slices and so on?

The Spartan 6 series' logic blocks are similar in structure, but the
LUTs have six address inputs instead of four and therefore are "worth
more" in terms of equivalent gates.

Chris
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