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'[EE] FPGA (Papilio)'
2011\04\08@060644 by V G

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Hi all,

I'm seriously considering getting myself a Papilio. This question is purely
out of curiosity. The $50 version has a Spartan 3E FPGA chip with 250K
gates.

What can I do with 250K gates? How many 8 bit CPU cores can I fit on there,
for example? How about an ARM 32 bit core? How many gates (approximately) do
these cores take?

What CAN and what CAN'T I do with 250K gates? Should I instead go for the
500K gates version? Or look for something else entirely?

The Spartan 3E series seem to be pretty cool (and cheap) chips. I checked
out other chips on Xilinx's and Altera's site and they seem to have some
seriously high end stuff on there. Just out of curiosity, how much would a
really high end FPGA cost?

I don't know anything about anything about FPGAs so please go easy on me. I
just have this feeling that Olin's going to attack me on the type of
question I'm asking.

MAXIMUM ARMOUR. Crysis (2) anyone

2011\04\08@062348 by Mike Harrison

flavicon
face
On Fri, 8 Apr 2011 06:06:29 -0400, you wrote:

>Hi all,
>
>I'm seriously considering getting myself a Papilio. This question is purely
>out of curiosity. The $50 version has a Spartan 3E FPGA chip with 250K
>gates.
>
>What can I do with 250K gates? How many 8 bit CPU cores can I fit on there,
>for example?
A few - onboard memory will probably be the first limit you hit

>How about an ARM 32 bit core? How many gates (approximately) do
>these cores take?

Maybe, or at least something similar - look at he gate counds for Xilinx Microblaze to get a feel
for usage

>What CAN and what CAN'T I do with 250K gates? Should I instead go for the
>500K gates version? Or look for something else entirely?

As above, memory may be more of an issue than gate. Also for complex designs teh compile process
will be quicker for a larger device as it doesn't have to try so hard to fit it.

>The Spartan 3E series seem to be pretty cool (and cheap) chips. I checked
>out other chips on Xilinx's and Altera's site and they seem to have some
>seriously high end stuff on there. Just out of curiosity, how much would a
>really high end FPGA cost?

Several thousand $ each., For example : search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=XC6VLX760-L1FFG1760I-ND

2011\04\08@064622 by alan.b.pearce

face picon face
> The Spartan 3E series seem to be pretty cool (and cheap) chips. I checked
> out other chips on Xilinx's and Altera's site and they seem to have some
> seriously high end stuff on there. Just out of curiosity, how much would a
> really high end FPGA cost?

Oh, well into the US$10,000 - but they are Rad Hard, ITAR limited, space approved, not available to everyone, export license limited ....
-- Scanned by iCritical.

2011\04\08@065427 by Herbert Graf

picon face
On Fri, 2011-04-08 at 06:06 -0400, V G wrote:
> Hi all,
>
> I'm seriously considering getting myself a Papilio. This question is purely
> out of curiosity. The $50 version has a Spartan 3E FPGA chip with 250K
> gates.
>
> What can I do with 250K gates?
Alot.

> How many 8 bit CPU cores can I fit on there,
> for example? How about an ARM 32 bit core? How many gates (approximately) do
> these cores take?

No idea. And any number I'd give you would be completely useless.

A "gate" isn't the same across FPGA families (or any other sort of
digital logic). The reason is there are no "gates" on FPGAs, just LUTs,
registered elements (flops/latches) and SRAM (both distributed and block
I believe in that FPGA). How many gates a bunch of LUTs is equivalent
too depends one what kind of logic you put into it.

The answer is: download the Xilinx webpack (free to download and use for
the smaller parts), target the FPGA you want, and compile the core
you've got. The tool will tell you how much of the FPGA you're using,
and use that to gauge what size part you need (if you start getting
tight there are tool options you can use to optimize for size or speed,
but you just want a rough number for the moment).


> The Spartan 3E series seem to be pretty cool (and cheap) chips.
Spartan 3s are pretty full featured, they share the architecture of I
believe the Virtex 2 Pros, so alot of features in those parts are
available to you.

> I checked
> out other chips on Xilinx's and Altera's site and they seem to have some
> seriously high end stuff on there. Just out of curiosity, how much would a
> really high end FPGA cost?

Can't give you specific pricing, but if you're targeting the largest
parts you start reaching the $10k mark, per device.

TTYL

2011\04\08@072052 by Oli Glaser

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face
On 08/04/2011 11:06, V G wrote:
> Hi all,
>
> I'm seriously considering getting myself a Papilio. This question is purely
> out of curiosity. The $50 version has a Spartan 3E FPGA chip with 250K
> gates.
>
> What can I do with 250K gates? How many 8 bit CPU cores can I fit on there,
> for example? How about an ARM 32 bit core? How many gates (approximately) do
> these cores take?

A small 8-bit core will be a few tens of K - IIRC, the one I am using currently on a ProASIC3 takes about 20K gates, but depends on the settings (you can select different bus widths, whether to enable certain instructions etc) FPGA cores like Picoblaze and CoreABC(Actel) are designed for size/efficiency so are very simple. To get similar to e.g. 16F functionality you need more gates - for example IIRC an (Actel) 8051 core with no peripherals takes around 60K gates (again depending on settings, but I remember the smallest setup not quite fitting on a 60K device) but you can use the Keil C compiler for it (as opposed to a small popup screen for assembler for the CoreABC - not sure about the Picoblaze though)
Remember you also need RAM, and somewhere to store your program - on the ProASIC you can store instructions in FPGA registers for the CoreABC and use the onboard RAM, but for the 8051 you need an off chip store. I'm not sure how Xilinx do things (probably very similar) but if you are getting a dev board it will likely be setup so you can try various things out easily.
If you want a good idea of what 250K gates will do, read some of the Xilinx core datasheets (counters, adders, UART, SPI, Picoblaze etc)  They should have info on how many gates they take, what speed they can run at and so on.


> What CAN and what CAN'T I do with 250K gates? Should I instead go for the
> 500K gates version? Or look for something else entirely?

250K gates will do plenty, I would go for that (I started with 60K and it was more than enough to learn with)

> The Spartan 3E series seem to be pretty cool (and cheap) chips. I checked
> out other chips on Xilinx's and Altera's site and they seem to have some
> seriously high end stuff on there. Just out of curiosity, how much would a
> really high end FPGA cost?
>
> I don't know anything about anything about FPGAs so please go easy on me. I
> just have this feeling that Olin's going to attack me on the type of
> question I'm asking.
>
> MAXIMUM ARMOUR. Crysis (2) anyone?

2011\04\08@074442 by V G

picon face
On Fri, Apr 8, 2011 at 6:23 AM, Mike Harrison <spam_OUTmikeTakeThisOuTspamwhitewing.co.uk> wrote:

>  A few - onboard memory will probably be the first limit you hit
>

Thanks. I'll look for memory upgrade options.

As above, memory may be more of an issue than gate. Also for complex designs
> teh compile process
> will be quicker for a larger device as it doesn't have to try so hard to
> fit it.
>

Is compile time *actually* an issue? I mean, to compile a C program in C32,
it takes less than a second or so. How long would it take to compile an FPGA
program when the compiler is trying hard to fit it? How long does it take on
average?


> Several thousand $ each.,
> For example :
>
> http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=XC6VLX760-L1FFG1760I-ND
>

Whoah. Why? As in, what features/performance/whatever do you get for a $20
000 chip

2011\04\08@080134 by Mike Harrison

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face
On Fri, 8 Apr 2011 07:44:27 -0400, you wrote:

>On Fri, Apr 8, 2011 at 6:23 AM, Mike Harrison <.....mikeKILLspamspam@spam@whitewing.co.uk> wrote:
>
>>  A few - onboard memory will probably be the first limit you hit
>>
>
>Thanks. I'll look for memory upgrade options.
>
>As above, memory may be more of an issue than gate. Also for complex designs
>> teh compile process
>> will be quicker for a larger device as it doesn't have to try so hard to
>> fit it.
>>
>
>Is compile time *actually* an issue? I mean, to compile a C program in C32,
>it takes less than a second or so. How long would it take to compile an FPGA
>program when the compiler is trying hard to fit it? How long does it take on
>average?

Compiling a FPGA is many orders of magnitude more work than compiling code. A vague analogy is compiling a description of a circuit board containing tens of thousands of parts
into a finished PCB layout. It has to not only parse your code into logic, it then has to place and route it on the FPGA's
resources, and do timing analysis, then often rip-up and repeat the process as necessary until it
meets timing requirements, which means the time can increase exponentially as the device approaches
capacity.

30 secs would be a typical bare-minimum compile time for a trivial design on a fast PC, due to the
number of different tools that are needed for the whole process. Hours or even days are not uncommon
for  high-end stuff on a fairly full device.

>> Several thousand $ each.,
>> For example :
>>
>> search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=XC6VLX760-L1FFG1760I-ND
>>
>
>Whoah. Why? As in, what features/performance/whatever do you get for a $20
>000 chip?

A massive piece of silicon with an  awful lof of gates and pins....

2011\04\08@083050 by Michael Watterson

face picon face
On 08/04/2011 12:44, V G wrote:
> Is compile time*actually*  an issue? I mean, to compile a C program in C32,
> it takes less than a second or so. How long would it take to compile an FPGA
> program when the compiler is trying hard to fit it? How long does it take on
> average?

Completely different kind of problem. The "FPGA" compile is more like generating a Schematic of a motherboard from a specification and then trying to auto-route the connections without moving the chips. It's not exactly that, but more like. In comparison Compiler from C to Assembler is very very simple and much older tool.

It's not a program that maps to run-time instructions. The FPGA design is really a specification. Each part of it maps to a selection of gates or logic that can be implemented by a RAM lookup table (no runtime instructions), physical Multipliers, physical PLLs, physical registers/latches and I/O port configurations .

There is an ARM M0 softcore, that uses most of a cheap FPGA. 6502, Z80 etc cores are available. These are really HW definitions. There is a new FPGA that has a pair of real HW ARM Cortex cores.

As well as RAM for LUT, there are other blocks of RAM.

You can also design an interface in the FPGA design to use external Flash, DRAM and/or Static RAM. The Spartan 3E starter kit has external physical RAM, Flash, ethernet PHY etc..

Also most FPGA need the definition loaded from Flash or CPU at power on. Again, unlike a CPU executing a Program from Flash, the entire "file" is loaded before the FPGA is functional at all. There is no "run time" code execution at all in sense of C to Assembler or C#/Java/Forth to Virtual Machine (unless there is soft CPU defined). You can view the synthesised FPGA design as a HW schematic and in theory build that.

An ASIC replacing a FPGA in Production volume, does approximately just that, replacing the general purpose "lego" of the FPGA with custom gates and layout connections. The FPGA is like a breadboard where your design sort of adds connections between many standard parts and "buses".



2011\04\08@083305 by Michael Watterson

face picon face
On 08/04/2011 12:20, Oli Glaser wrote:
>> >  What can I do with 250K gates? How many 8 bit CPU cores can I fit on there,
>> >  for example? How about an ARM 32 bit core? How many gates (approximately) do
>> >  these cores take?
> A small 8-bit core will be a few tens of K - IIRC, the one I am using
> currently on a ProASIC3 takes about 20K gates, but depends on the
> settings (you can select different bus widths, whether to enable certain
> instructions etc) FPGA cores like Picoblaze and CoreABC(Actel) are
> designed for size/efficiency so are very simple. To get similar to e.g.
> 16F functionality you need more gates - for example IIRC an (Actel) 8051
> core with no peripherals takes around 60K gates (again depending on
> settings, but I remember the smallest setup not quite fitting on a 60K
> device) but you can use the Keil C compiler for it (as opposed to a
> small popup screen for assembler for the CoreABC - not sure about the
> Picoblaze though)

Also don't even think about Floating Point!
(usually).

If you need a CPU and Floating point, buy one and interface it to the FPGA!

2011\04\08@083550 by Oli Glaser

flavicon
face
On 08/04/2011 12:44, V G wrote:
> Whoah. Why? As in, what features/performance/whatever do you get for a $20
> 000 chip?

Much of the price is simply because they are the cutting edge (have a look what a 250K gate FPGA cost say, 5 years ago) in a few years (provided things carry on approximating Moore's law) they will be available for $50 and there will be another chip 10 times as large again.
Apart from sheer size (>10M gates) they will have stuff like the latest/fastest transceivers, onboard ARM/DSP/analogue hardware, loads and loads of RAM, and so on.
The cutting edge is a very expensive place to be.. :-)

2011\04\08@094816 by k c

picon face
V G wrote:
>
> I'm seriously considering getting myself a Papilio. This question is purely
> out of curiosity. The $50 version has a Spartan 3E FPGA chip with 250K
> gates.
>
> What can I do with 250K gates?

Why not trying to emulate a basic neural network

2011\04\08@101722 by Tamas Rudnai

face picon face
On Fri, Apr 8, 2011 at 11:06 AM, V G <x.solarwind.xspamKILLspamgmail.com> wrote:

> I don't know anything about anything about FPGAs so please go easy on me. I
> just have this feeling that Olin's going to attack me on the type of
> question I'm asking.
>

In my opinion you only got attacked when you did not do your homework. For
example questions like 'how many 8 bit CPU can be done' feels a bit like
that -- you obviously have not got any experience on constructing a CPU so
you should have study this instead asking the question -- for example just
get that board for yourself and start building it and you will see how many
gates you need for this or that. Then you will see that there is no 'an 8
bit CPU' but there are specific CPUs, one need more, the other one need less
components.

I (and presume many others here) admire your passion about electronics and
PICs but in the meanwhile I really feel instead of jumping from one project
to another you should need to spend more time on one thing to learn properly
and of course read more before asking a question. That would be the biggest
*armour*against*attacks* you might get here.

The other thing is that you keep creating new and new threads for the very
same subject even if you have just an update or a new question about the
same thing. It makes really hard to follow up what have you done so far, and
that leads to attacks as one might have not seen your older post as it was
in a different thread, therefore assuming that you missed out some steps
which you might have done already. Also it makes harder to follow up the
learning curve you make as cannot mark the thread to follow as you change
it, or cannot ignore the thread by the very same reason.

Tamas





>
> MAXIMUM ARMOUR. Crysis (2) anyone?
>

2011\04\08@104747 by Herbert Graf

picon face
On Fri, 2011-04-08 at 07:44 -0400, V G wrote:
> On Fri, Apr 8, 2011 at 6:23 AM, Mike Harrison <.....mikeKILLspamspam.....whitewing.co.uk> wrote:
>
> >  A few - onboard memory will probably be the first limit you hit
> >
>
> Thanks. I'll look for memory upgrade options.

The options are get a bigger FPGA, trying to tack on memory gets very
messy very quickly, and much more pricey (unless you need many MBs of
memory)

{Quote hidden}

Sorry, but that question has no answer, there is no average.

The time it takes to gets bits for an FPGA depends on many things, a
SMALL subset is:

- the size of the FPGA
- the architecture of the FPGA
- the version of the compiler
- the size of your design
- how tightly you constrain your design
- how completely you constrain your design
- the speed of your computer
- the speed of your FPGA

For a Spartan 3E, saying you choose a 1000 part and you have it
relatively full, you're probably looking at up to an hour. As a minimum
you'll be looking at at least a few minutes.

For bigger parts it can take a day.

>
> > Several thousand $ each.,
> > For example :
> >
> > search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=XC6VLX760-L1FFG1760I-ND
> >
>
> Whoah. Why? As in, what features/performance/whatever do you get for a $20
> 000 chip?

Size. The LX760 is the biggest part available right now, you can cram
ALOT of stuff on that chip.

As for the $20k, lets just say that few would buy this part from
Digikey.

TTYL

TTYL

2011\04\08@110049 by M.L.

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face

On Fri, Apr 8, 2011 at 10:47 AM, Herbert Graf <EraseMEhkgrafspam_OUTspamTakeThisOuTgmail.com> wrote:
> On Fri, 2011-04-08 at 07:44 -0400, V G wrote:
>> On Fri, Apr 8, 2011 at 6:23 AM, Mike Harrison <mikespamspam_OUTwhitewing.co.uk> wrote:
>>
>> >  A few - onboard memory will probably be the first limit you hit
>> >
>>
>> Thanks. I'll look for memory upgrade options.
>
> The options are get a bigger FPGA, trying to tack on memory gets very
> messy very quickly, and much more pricey (unless you need many MBs of
> memory)
>


It can be "tricky" depending on how you do it. It's quite easy to
interface to the parallel SRAM that Digilent puts on their boards.
http://digilentinc.com/Products/Detail.cfm?NavPath=2,400,789&Prod=NEXYS2

On the other hand SDRAM is quite complex.

--
Martin K.

2011\04\08@120907 by Dave Tweed

face
flavicon
face
Herbert Graf wrote:
> On Fri, 2011-04-08 at 07:44 -0400, V G wrote:
> > On Fri, Apr 8, 2011 at 6:23 AM, Mike Harrison <@spam@mikeKILLspamspamwhitewing.co.uk> wrote:
> >
> > >  A few - onboard memory will probably be the first limit you hit
> > >
> >
> > Thanks. I'll look for memory upgrade options.
>
> The options are get a bigger FPGA, trying to tack on memory gets very
> messy very quickly, and much more pricey (unless you need many MBs of
> memory)

Sorry, but I think that's bad advice. For a given amount of memory, it's much
cheaper to use external memory than on-chip memory.

Pretty much every FPGA development board I've seen has some amount of external
memory attached to the FPGA, whether it be static (async) SRAM, synchronous
SRAM, or SDR/DDR SDRAM. (Unfortunately, it looks like Papilio is one of the
exceptions.) And all of the major FPGA vendors have memory controller modules
built into their design environments. Granted, sometimes it can be tricky to
get them to work properly, depending on how good the documentation is.

The tradeoff is, with on-chip memory you get relatively small amounts of
storage, but very low latency and very high bandwidth (you can access all of
the memories in parallel, if necessary). With off-chip memory, you get
potentially huge amounts of storage (100s of MB, or even GBs if you go with
computer memory modules), but you have to deal with relatively long (and
possibly variable) latencies, and limited bandwidth (but still in the GB/sec
range).

One of my specialties is doing real-time high-definition video signal
processing in FPGAs. There's just no way to fit a multi-megapixel frame buffer
into any reasonably-priced FPGA, so I'm always dealing with external memory,
usually DDR SDRAM. My biggest problem is that I usually have multiple "users"
of that memory inside the FPGA, e.g., raw video buffers, pixel correction
maps, time-domain filter states, graphic overlay buffer, etc. So, I've had to
develop a way to multiplex the memory controller among the various requesters,
usually using the on-chip memory as FIFOs to decouple the timing of the video
pipeline from that of the memory controller itself. It all works fine, as long
as you're careful not to over-subscribe the available bandwidth.

Anyway, getting back to the original question of "how many CPUs on an FPGA",
it looks like with the Papilio One platform, you'd need to develop a custom
"wing" to add external memory. On-chip CPUs that use only on-chip memory tend
to be smaller 8-bit designs with Harvard architectures (one memory block for
code, another for data) such as the Xilinx Picoblaze, which uses a few hundred
logic "cells" (LUT plus flip-flop) in addition to the block RAMs. As Mike
said, you'll probably run out of block RAM before you run out of logic cells.
On the '250E (12 block RAMs), you'd get 6 CPUs, and on the '500E (20 block
RAMs), you'd get 10 CPUs. Each CPU would get 2KB of code space and 2KB of data
space. On the plus side, you could also give each CPU a dedicated hardware
multiplier, making it a good system for doing some serious DSP. But, putting
this into perspective, the '500E configured with 10 CPUs would be roughly
equivalent to a Parallax Propeller chip, yet it costs a lot more and consumes
much more power.

-- Dave Twee

2011\04\08@123217 by Denny Esterline

picon face
On Fri, Apr 8, 2011 at 7:17 AM, Tamas Rudnai <KILLspamtamas.rudnaiKILLspamspamgmail.com> wrote:
> On Fri, Apr 8, 2011 at 11:06 AM, V G <RemoveMEx.solarwind.xTakeThisOuTspamgmail.com> wrote:
>
>> I don't know anything about anything about FPGAs so please go easy on me.. I
>> just have this feeling that Olin's going to attack me on the type of
>> question I'm asking.
>>
>
> In my opinion you only got attacked when you did not do your homework. For
> example questions like 'how many 8 bit CPU can be done' feels a bit like
> that -- you obviously have not got any experience on constructing a CPU so
> you should have study this instead asking the question -- for example just
> get that board for yourself and start building it and you will see how many
> gates you need for this or that. Then you will see that there is no 'an 8
> bit CPU' but there are specific CPUs, one need more, the other one need less
> components.
>

Interesting.... The "attack" part aside, I come in on the other side
of this. When your just beginning getting your head around something,
I think it's very useful to ask questions about the "landscape" of
something. Yes, something like "how many 8-bit CPUs can I fit in X
gates" is very vague. But even the equally vague answers have been
quite enlightening. Answers like "several" and "you'll run out of
memory first" give a definite feel for the subject.

The old saying goes, when the only tool you have is a hammer, every
problem looks like a nail. Extending that, this question becomes: is
this tool a tack hammer or a 3 ton wrecking ball? :-)

-Denn

2011\04\08@131428 by Michael Watterson

face picon face
On 08/04/2011 17:32, Denny Esterline wrote:
> I think it's very useful to ask questions about the "landscape" of
> something. Yes, something like "how many 8-bit CPUs can I fit in X
> gates" is very vague. But even the equally vague answers have been
> quite enlightening. Answers like "several" and "you'll run out of
> memory first" give a definite feel for the subject.

I agree

And one answer is that it's the wrong question!

As FPGAs are very good for stuff that CPUs can't do well, or can only do 10,000x slower.

Just one soft CPU core, or even a separate PIC or ARM interfaced is more likely a better use

2011\04\08@174703 by Christopher Head

picon face

On Fri, 08 Apr 2011 06:54:21 -0400
Herbert Graf <spamBeGonehkgrafspamBeGonespamgmail.com> wrote:

> The answer is: download the Xilinx webpack (free to download and use
> for the smaller parts), target the FPGA you want, and compile the core
> you've got. The tool will tell you how much of the FPGA you're using,
> and use that to gauge what size part you need (if you start getting
> tight there are tool options you can use to optimize for size or
> speed, but you just want a rough number for the moment).

Do remember though that while the percentage full is a nice guide, it's
not quite the whole truth. With the Xilinx tools, anyway, when the
slice usage reaches 99%, you can still add some more logic, it will
just make the compiler run more slowly as it works harder to pack
things tightly, and you may also end up running out of clock frequency
before you actually run out of slices. So you can't just say “Oh, 53%
full, I guess I can't put another <whatever> on this FPGA”. In that
case, you probably could fit another <whatever>, but it'll take longer
to compile and you might be limited in what frequency of oscillator you
can run the resulting system on.

Chris

2011\04\08@202015 by Herbert Graf

picon face

On Fri, 2011-04-08 at 14:46 -0700, Christopher Head wrote:
> Do remember though that while the percentage full is a nice guide, it's
> not quite the whole truth. With the Xilinx tools, anyway, when the
> slice usage reaches 99%, you can still add some more logic, it will
> just make the compiler run more slowly as it works harder to pack
> things tightly, and you may also end up running out of clock frequency
> before you actually run out of slices. So you can't just say “Oh, 53%
> full, I guess I can't put another <whatever> on this FPGA”. In that
> case, you probably could fit another <whatever>, but it'll take longer
> to compile and you might be limited in what frequency of oscillator you
> can run the resulting system on.

Very true, which is why we never use slice usage as a determination of
"fullness".

The reason is slices can be "used", even if they are just used for pass
through routes.

A far better metric we've found with Xilinx parts is LUT usage.
Generally, you will have no problems getting a design to finish
(assuming you're reasonable with your timing constraints) as long as you
are below 70%. Between 70% and 80% you will likely have no problems, but
compile times will rise dramatically. Above 80% you are pretty much
overfilling the part, it will likely never finish compiling, and if it
does chances are your constraints won't be met. We generally ensure none
of our designs are above 75% LUT usage.

This of course is ignoring other reasons a part might be "full". Another
poster had mentioned memories, if you run out of blockram then your part
will be "full" well before you run out of LUTs.

I've never seen a design that stressed the registered elements, but I'm
sure there can be cases.

Clock resources can also be an issue, if you have multiple domains, or
do clock gating in "bad" ways you can easily run out of clocks (in fact
a good sign you are doing something bad with clocks is if you run out of
BUFGs, or are using many more BUFGs then the clocks you think you are
using).

DSPs can be an issue in some parts. If you have alot of math related
logic you might hit a wall since the tools will infer DSPs for those
math functions; the moment you run out of DSP blocks your usage will
accelerate because regular LUTs are now being used to implement the math
functions.

All that said, if this is not a production environment things aren't as
critical, use the tools to see which part you'll fit in, and then get
the next biggest part to be safe.

TTYL


2011\04\09@014152 by William \Chops\ Westfield

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On Apr 8, 2011, at 3:23 AM, Mike Harrison wrote:

>> how much would a really high end FPGA cost?

I have some "found" chips that are probably Xilinx XCV1600E-8FG1156C  FPGAs (that doesn't match the packaging exactly, and I'm not willing  to open the sealed packet to see what's on the chips.)
search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=XCV1600E-8FG1156C-ND
2 million gates, 1156 balls (pins), worth nearly $4000 each, according  to digikey.

Useless bits of trash; apparently.  I tried to find a home for them  (near where they were "found") and was told approximately: 0) they  only cost us about $800.  1) we can't transfer them from "found" to  "production use" anyway.  2) they're obsolete, and so of no use on the  development side of things.  3) Approximately equivalent current- generation chips are MUCH cheaper.  And *I* certainly can't use them.   1156 balls!  OMG!

Sigh.
BillW

2011\04\10@093623 by V G

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Sorry for not trimming.

How much cheaper are equivalent current generation chips?

Also, would you guys recommend the papilio 250K board? Or would you
guys recommend another?

On Saturday, April 9, 2011, William "Chops" Westfield <TakeThisOuTwestfwEraseMEspamspam_OUTmac.com> wrote:
{Quote hidden}

>

2011\04\10@095728 by Xiaofan Chen

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On Sun, Apr 10, 2011 at 9:36 PM, V G <RemoveMEx.solarwind.xspamTakeThisOuTgmail.com> wrote:
> Sorry for not trimming.
>
> How much cheaper are equivalent current generation chips?
>
> Also, would you guys recommend the papilio 250K board? Or would you
> guys recommend another?

I attended an one-day training by Arrow and their BeMicro board
seems to be quite good.
http://www.altera.com/b/nios-bemicro-evaluation-kit.html

The good thing about it is that they have already the embedded
process ready (Nios-II) and the Eclipse/GCC based toolchain
ready. The bad thing is that it seems to need the subscription
edition which you can only get free evaluation license for
30 days. At least that is what was used in the training.

-- Xiaofa

2011\04\10@143612 by Oli Glaser

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On 10/04/2011 14:36, V G wrote:
> How much cheaper are equivalent current generation chips?
>
> Also, would you guys recommend the papilio 250K board? Or would you
> guys recommend another?
>

I would recommend pretty much anything with a reasonably recent FPGA on, and easy access to the pins. I haven't looked, but the Papillo sounds fine to me.
I started with a 60K device and just made my own simple board, which did little more than provide a clock source and make pins accessible. It was absolutely fine for learning purposes, as there are endless things to try out on the chip itself, and then provide a simple debug result on the pins. If you need to (e.g. if designing a UART) you can connect to other things anyway using a breadboard.
For instance if you are designing an ALU, all your work is on board the chip, and the result can be as simple as a bunch of LEDs (or display on a logic analyser) Also, you be running things on the simulator many times before you route the FGPA anyway, so you will get a good feel for what's going on there.
This is a bit different to working with uCs as you assume the silicon is working to start with. With an FPGA you are designing the "silicon" itself, which is a huge and complex field. Hopefully this makes some sense - roughly my point is don't worry too much about dev board features, there will be plenty to try with the most simple available, so grab something and start from the beginning. This is probably a better approach, as you will not be as tempted to try out all the fancy stuff before you understand the "basics". Just learning how to use the tools will keep you occupied for a while.. :-)

2011\04\10@151612 by V G

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On Sun, Apr 10, 2011 at 2:35 PM, Oli Glaser <oli.glaserEraseMEspam.....talktalk.net> wrote:

{Quote hidden}

Thanks! I'm probably going to go with the Nexys2
http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS2 since I've read
that there is a lot of documentation and support for it. Also has on board
flash and RAM as well as high speed USB2

2011\04\10@155628 by Oli Glaser

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On 10/04/2011 20:15, V G wrote:
> Thanks! I'm probably going to go with the Nexys2
> http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS2  since I've read
> that there is a lot of documentation and support for it. Also has on board
> flash and RAM as well as high speed USB2.

Looks like a very good choice, and a good price - the available textbooks written specially for the board will make life easier, I would grab one of those too (if your budget stretches that far - web based examples are a lot scarcer than with microcontrollers)

2011\04\10@161025 by Michael Watterson

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On 10/04/2011 20:55, Oli Glaser wrote:
> On 10/04/2011 20:15, V G wrote:
>> Thanks! I'm probably going to go with the Nexys2
>> http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS2  since I've read
>> that there is a lot of documentation and support for it. Also has on board
>> flash and RAM as well as high speed USB2.
> Looks like a very good choice, and a good price - the available
> textbooks written specially for the board will make life easier, I would
> grab one of those too (if your budget stretches that far - web based
> examples are a lot scarcer than with microcontrollers)
>
I got this one
http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,792&Prod=S3EBOARD

from Germany at a similar price.

Both boards will work with most of the freely available and plentiful Spartan-3e tutorials.

you can replace Matlab by Scilab and script to make a .coe file of DSP coefficients for the free Xilinx tools

2011\04\11@001235 by V G

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On Sun, Apr 10, 2011 at 4:10 PM, Michael Watterson <EraseMEmikespamradioway.org>wrote:

> from Germany at a similar price.
>
> Both boards will work with most of the freely available and plentiful
> Spartan-3e tutorials.
>
> you can replace Matlab by Scilab and script to make a .coe file of DSP
> coefficients for the free Xilinx tools


Thanks for the advice! I'll check it out

2011\04\15@035656 by k c

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V G wrote:
>
> Thanks! I'm probably going to go with the Nexys2
> http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS2 since I've read
> that there is a lot of documentation and support for it. Also has on board
> flash and RAM as well as high speed USB2.
> --

You may use it with Cypress Semiconductor’s new EZ-USB (Universal
Serial Bus) FX3 for USB 3.0 applications. It combines a flexible
peripheral controller with a USB 3.0 PHY (physical) interface that
provides a data pipeline as fast as 5 Gbps. Or wait for LightSpeed /
Thunderbolt.

2011\04\15@041732 by Xiaofan Chen

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On Fri, Apr 15, 2011 at 3:56 PM, k c <RemoveMEkaikoura.canyonEraseMEspamEraseMEgmail.com> wrote:
> You may use it with Cypress Semiconductor’s new EZ-USB (Universal
> Serial Bus) FX3 for USB 3.0 applications. It combines a flexible
> peripheral controller with a USB 3.0 PHY (physical) interface that
> provides a data pipeline as fast as 5 Gbps. Or wait for LightSpeed /
> Thunderbolt.

That is probably too early. Most of the current generation
FPGA uses EZ-USB FX2LP (high speed USB). Interestingly
the limit for the FX2LP is the slow 8051 MCU core, so it
is rather a intelligent peripheral controller with a slow MCU
core but not a real high speed USB 2.0 MCU.

In the case of EZ-USB FX3, it now comes with a 200MHz
ARM926EJS core, quite good, but still not a real
super-speed USB MCU since that is still too slow
compared to 5Gbps USB 3.0.
http://www.edn.com/article/517788-USB_3_0_controller_embeds_microcontroller_for_customized_applications.php

On the other hand, even though I have bought two
USB 3.0 external hard disks, none of my PCs
come with USB 3.0 host controller (XHCI), so I
do not know how good USB 3.0 is.

-- Xiaofan

2011\04\15@045753 by Michael Watterson

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On 15/04/2011 09:17, Xiaofan Chen wrote:
> On the other hand, even though I have bought two
> USB 3.0 external hard disks, none of my PCs
> come with USB 3.0 host controller (XHCI)

For Random Access, an HD might just beat USB 1.1

Only bursts to or from the on-board controller cache can exhaust the speed of USB 2.0 on a single drive.

Drives are natively faster toward edge of platter. Native block transfer sequential speed (excluding track to track stepping or random access) is limited by rotational speed and bit density. For larger transfers, even without Random Access, the track to track delay is very high.

USB 2 is worthwhile. I'm sceptical that USB 3.0 is needed for ordinary single drives

2011\04\15@054636 by Xiaofan Chen

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On Fri, Apr 15, 2011 at 4:57 PM, Michael Watterson <RemoveMEmikespam_OUTspamKILLspamradioway.org> wrote:
> On 15/04/2011 09:17, Xiaofan Chen wrote:
>> On the other hand, even though I have bought two
>> USB 3.0 external hard disks, none of my PCs
>> come with USB 3.0 host controller (XHCI)
>
> For Random Access, an HD might just beat USB 1.1
>
> Only bursts to or from the on-board controller cache can exhaust the
> speed of USB 2.0 on a single drive.
>
> Drives are natively faster toward edge of platter. Native block transfer
> sequential speed (excluding track to track stepping or random access) is
> limited by rotational speed and bit density. For larger transfers, even
> without Random Access, the track to track delay is very high.
>
> USB 2 is worthwhile. I'm sceptical that USB 3.0 is needed for ordinary
> single drives.

Just look at a simple benchmark comparison here.
http://www.notebookreview.com/default.asp?newsID=5761&p=2

Or more comprehensive result here.
http://www.tomshardware.com/charts/usb-3.0-storage-charts/benchmarks-2,108.html

Then you will understand why USB 3.0 is necessary.

-- Xiaofa

2011\04\15@065923 by Tamas Rudnai

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If I think it over, back in the early 90's when I replaced my 40MB HDD to
an enormous 120MB one, I could not even fill it up -- and now I could copy
the entire disk in 1 sec!

Tamas



On Fri, Apr 15, 2011 at 10:46 AM, Xiaofan Chen <RemoveMExiaofancTakeThisOuTspamspamgmail.com> wrote:

{Quote hidden}

>

2011\04\15@072032 by Michael Watterson

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On 15/04/2011 11:59, Tamas Rudnai wrote:
> If I think it over, back in the early 90's when I replaced my 40MB HDD to
> an enormous 120MB one, I could not even fill it up -- and now I could copy
> the entire disk in 1 sec!
>
> Tamas
>

My 1st HDD was a 5Mbyte model with it's own PSU on an Apple II, in 1981 or 1982. Running CP/M on a Z80 card, so not really an Apple II. The last Apple product I've bought, though I have maintained machines with OS9 and OSX for others.

2011\04\15@080514 by V G

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Sorry for not trimming.

Are you referring to just buying the module and hooking it up to the
FPGA? If so, couldnt I do that with pretty much any modern FPGA? Why
specifically the Nexys2 board?

On Friday, April 15, 2011, k c <RemoveMEkaikoura.canyonKILLspamspamgmail.com> wrote:
{Quote hidden}

>

2011\04\15@101508 by Herbert Graf

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On Fri, 2011-04-15 at 09:57 +0100, Michael Watterson wrote:
> On 15/04/2011 09:17, Xiaofan Chen wrote:
> > On the other hand, even though I have bought two
> > USB 3.0 external hard disks, none of my PCs
> > come with USB 3.0 host controller (XHCI)
>
> For Random Access, an HD might just beat USB 1.1
>
> Only bursts to or from the on-board controller cache can exhaust the
> speed of USB 2.0 on a single drive.
>
> Drives are natively faster toward edge of platter. Native block transfer
> sequential speed (excluding track to track stepping or random access) is
> limited by rotational speed and bit density. For larger transfers, even
> without Random Access, the track to track delay is very high.
>
> USB 2 is worthwhile. I'm sceptical that USB 3.0 is needed for ordinary
> single drives.

I'm not sure why you say that.

Pretty much ANY modern drive will EASILY saturate a USB2 connection. The
fastest most people can transfer over USB2.0 is about 30MBps, it's been
a while since a hard drive was that slow.

I regularly transfer many GBs of data over a USB2 connection (an
external USB harddrive for offsite backups), I can't wait for USB3 to be
more common.

TTYL

2011\04\15@142927 by Oli Glaser

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On 15/04/2011 15:14, Herbert Graf wrote:
{Quote hidden}

Me neither, could you explain this?
Although seek times are pretty slow, the average sustained disk to buffer rate for a 7200 rpm desktop drive according to the Wiki page is around 1030 Mbits/s, so around 100MB/s. This will be higher for more advanced drives, e.g  10,000rpm.
http://en.wikipedia.org/wiki/Hard_disk_drive
I definitely notice a slower transfer rate when using my external USB 2.0 drive, compared to internal transfer.

2011\04\16@121656 by k c

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V G wrote:
>>
>> You may use it with Cypress Semiconductor’s new EZ-USB (Universal
>> Serial Bus) FX3 for USB 3.0 applications. It combines a flexible
>> peripheral controller with a USB 3.0 PHY (physical) interface that
>> provides a data pipeline as fast as 5 Gbps. Or wait for LightSpeed /
>> Thunderbolt.
>>
> Sorry for not trimming.
>
> Are you referring to just buying the module and hooking it up to the
> FPGA?

Yes

> If so, couldnt I do that with pretty much any modern FPGA?

Yes

> Why specifically the Nexys2 board?
>

None specifically the Nexys2 board, you can "do that with pretty much
any modern FPGA".

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