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'[EE]: Pulse circuit, can you explain how this work'
2003\04\19@115823 by James Williams

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Hello,

I have seen used in some circuits a delay pulse when a particular input
signal does high.  I.E.  The output of the circuit generates a short
pulse of 200 us when the input logic state goes 0, but then the output
goes high again even when the input is still low.

I can seen to figure out how this is working.  The circuit is a simple
inverter + a series capacitor to another inverter.  Also from the input
of the second invertor, between it's pin on the output of the capacitor,
a resistor is used to pull the pin to ground. The circuit looks
something like this:

IN ---|>o-----)|------|>o------ OUT
                  |
                  |_---/\/\/\/\--- GND

To me, the capacitor is acting as a coupling capacitor, so I fail to see
how this is making the output a small pulse given the input state.  Can
someone explain how this is producing a digital pulse on the output?

When I look at the circuit, it seems like no DC logic signal will get
through to the output.  When the input is low, the capacitor will charge
through the resistor.  Which leaves the output of the capacitor still at
ground level, correct?  Then when the input is high again, this causes
an instantaneous discharge of the capacitor, still leaving the output of
the capacitor at ground level, so I fail to see how this is used as a
way to generate a fixed length pulse when the input goes low.

What am I missing?

Regards,

James



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2003\04\19@121507 by Ned Konz

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On Saturday 19 April 2003 08:56 am, James Williams wrote:

{Quote hidden}

The fact that you've got a voltage divider. When the IN goes low, the
cap is still discharged (i.e. there's 0 volts across it). At that
instant, the resistor end is pulled high. However, that causes
current to flow into the capacitor. As the current flows, the cap
charges up, which means that the voltage across it increases. Shortly
after IN goes low, the capacitor is charged up to V+/2 or so, and the
voltage at the top of the resistor is at the threshold of the OUT
inverter. The signal then switches back to the quiescent state.

An even more amusing circuit uses the same RC network, but uses an
exclusive-OR gate to produce a pulse at *both* the low-to-high and
high-to-low transitions.

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2003\04\19@122537 by Larry Bradley

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What you have here is a "differentiator".  You are correct, no DC will get
through the capacitor.

But consider: initially, assume the input is high, thus the output of the
1st inverter is low. The input to the 2nd inverter is also low due to the
resistor, and thus the output of the 2nd inverter is high.

Now, the input goes low, the output of the inverter goes high, as does the
voltage on the left side of the capacitor. Since the voltage across the
capacitor cannot change instantaneously, the voltage on the right side of
the capacitor will go high also. The output of the 2nd inverter will now go
low.

As the capacitor charges through the resistor, the voltage on the input to
the 2nd inverter will start to drop exponentially - the time this will take
depends on the values of the resistor and capacitor. As the voltage drops,
it will reach a value that causes the 2nd inverter to think it's input is
now low, so the inverter output goes high.

Voila - a pulse, whose width depends on the values of R and C, and on the
voltage at which the 2nd inverter will change state. This pulse appears on
the falling edge of the input waveform.

When the input voltage goes high, the 1st inverter will go low; the right
side of the capacitor will follow suit, since the voltage can't change
instantaneously. Since the capacitor will have been fully charged by this
time (the voltage on its right side will be zero), the voltage on the right
side will go -ve, and will slowly increase towards zero as the capacitor
discharges through the resistor. This -ve voltage on the input of the 2nd
inverter will just leave the inverter's output high, thus there will be no
output pulse.

So what happens: on the rising edge of the input pulse, the output stays
low. On the falling edge of the input pulse, there will be a short pulse at
the output. So you have generated a pulse delayed by the width of the input
pulse.

Larry

At 11:56 AM 4/19/2003 -0400, you wrote:
{Quote hidden}

Larry Bradley
Orleans (Ottawa), Ontario, CANADA

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2003\04\19@122546 by James Williams

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How do you calculate the out pulse duration?  In my example, I have a
0.01uf cap and a 15Kohm resistor.  The book I am reading states that the
pulse is 200us, however when I calculate the RC time constant at the
first time interval, I only get 150us.  This should have caused the
circuit to have a pulse of 150us.  Because the first time interval is V
is at 67% charge leaving the voltage at 3.35 V.  Or did I miss something
else here too?

Regards,

James

{Original Message removed}

2003\04\19@124519 by Ned Konz

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On Saturday 19 April 2003 09:24 am, James Williams wrote:
> How do you calculate the out pulse duration?  In my example, I have
> a 0.01uf cap and a 15Kohm resistor.  The book I am reading states
> that the pulse is 200us, however when I calculate the RC time
> constant at the first time interval, I only get 150us.  This should
> have caused the circuit to have a pulse of 150us.  Because the
> first time interval is V is at 67% charge leaving the voltage at
> 3.35 V.  Or did I miss something else here too?
>

Yes, the threshold of the second inverter determines how far the cap
needs to charge.

If your second inverter switched at V+/3 you could indeed go for a
period of RC. However, it doesn't, probably, if it's CMOS.

So the period will be shorter, since the cap only has to charge over
50% of Vcc, not 67%.

The formula for the period is a simple exponential, since the rate of
cap charging depends on the voltage across the resistor. Assuming a
5V supply,

Vc = 5 * e ^ (-t/RC)

solving for Vc = 2.5 (the threshold for CMOS):

ln(0.5) = -t / RC
t = - ln(0.5) * RC
t = 0.693 RC

So your RC time constant of 150usec will result in a 104 usec pulse.

http://www.educatorscorner.com/media/Exp31.pdf

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2003\04\19@124929 by Larry Bradley

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The time constant RC is based on the voltage rising (or dropping) 67%.
However, the voltage at which the 2nd inverter changes state must be taken
into account. 67% of 5 volts is 3.35 volts, but if the 2nd invert changes
state at 4.2 volts, then the pulse width will be longer. If it switches at
2.5 volts, then it will be shorter. Since the threshold voltage is not
likely to be tightly specified for a particular inverter, and is likely to
be temperature dependent as well, this technique is probably not well
suited for precise pulse widths. But generally the pulse width doesn't
matter - this kind of thing is normally just used to get a delay, where the
output pulse is used to trigger something else.

Using the time constant as a rough guide to the pulse width is "good enough
for engineering purposes"

Larry

At 12:24 PM 4/19/2003 -0400, you wrote:
{Quote hidden}

Larry Bradley
Orleans (Ottawa), Ontario, CANADA

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2003\04\19@131958 by Ned Konz

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On Saturday 19 April 2003 09:44 am, Iwrote:

> The formula for the period is a simple exponential, since the rate
> of cap charging depends on the voltage across the resistor.
> Assuming a 5V supply,
>
> Vc = 5 * e ^ (-t/RC)
>

Sorry, that's the voltage across the resistor (quick sanity check:
t = 0, voltage = 5; t = many, voltage = 0).

Anyway, there are several problems with this circuit:

* the period depends on the threshold of the second inverter

* the current from the cap will end up going through the input
protection diodes of the second inverter when the first inverter's
output goes back to LOW. Whether this is a problem for you depends on
the size of the capacitor. You might add a diode and resistor to help
in this case.

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2003\04\19@132616 by James Williams

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<<snip>>
>An even more amusing circuit uses the same RC network, but uses an
>exclusive-OR gate to produce a pulse at *both* the low-to-high and
>high-to-low transitions.

How is the input pulse tied to an exclusive or to generate a pulse on
both the leading and trailing edge?

Regards,

James

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2003\04\19@134055 by Ned Konz

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On Saturday 19 April 2003 10:25 am, James Williams wrote:
> <<snip>>
>
> >An even more amusing circuit uses the same RC network, but uses an
> >exclusive-OR gate to produce a pulse at *both* the low-to-high and
> >high-to-low transitions.
>
> How is the input pulse tied to an exclusive or to generate a pulse
> on both the leading and trailing edge?


The input pulse (probably through an inverter) is tied directly to one
of the XOR inputs.

The other XOR input is connected to the common point of an RC network.
The capacitor's free end is connected to ground or V+.

The resistor's free end is connected also to the input pulse.

So the XOR input connected to the RC network is seeing a slightly
delayed version of the original pulse. During the period where the
levels are different (i.e. during the delay), the XOR output is true.

This doesn't suffer from the input-diode current problem that the
series capacitor circuits suffer from.

If you don't need a very long pulse, you can use a couple of inverters
in series to provide the delay.

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2003\04\20@074848 by Olin Lathrop

face picon face
> IN ---|>o-----)|------|>o------ OUT
>                    |
>                    |_---/\/\/\/\--- GND
>
> To me, the capacitor is acting as a coupling capacitor, so I fail to see
> how this is making the output a small pulse given the input state.  Can
> someone explain how this is producing a digital pulse on the output?

The C and R form a high pass filter into the second inverter.  In a rough
sense, this means edges get thru but steady levels don't.

Start with the circuit with IN high and steady state.  IN goes low, causing
a rising edge into the capacitor.  This step is coupled immediately to the
output inverter, making it go low.  So far, the signal has just been passed
thru.  Now consider what happens as IN stays low.  The input to the
capacitor stays high, but the output will exponentially decay towards 0.
This decaying voltage will eventually be interpreted as a low input by the
second inverter, making it go high.  We have so far sent a falling edge in
and gotten a low going pulse out.  In other words, and edge to glitch
converter.

Now IN goes high.  This causes the input to the capacitor to go low.  The
output of the capacitor is already at 0, so it will attempt to go to -5V.
However, the input clamping diode in the second inverter will clip that
to -700mV or so.  The output is not changed, but now we're ready for IN to
go low again and cause another pulse.

This type of circuit is somewhat of a kludge.  Wanting an edge to glitch
converter is usually a symptom of bad design elsewhere.  Note also that the
second inverter should be a schmitt trigger unless the RC time constant is
very low.

As an additional exercise, consider what the circuit does if R and C are
exchanged.


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2003\04\20@080341 by Olin Lathrop

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> How do you calculate the out pulse duration?  In my example, I have a
> 0.01uf cap and a 15Kohm resistor.  The book I am reading states that the
> pulse is 200us, however when I calculate the RC time constant at the
> first time interval, I only get 150us.

The time constant is indeed 10nF x 15Kohm = 150uS.  This is the time it
takes for the exponential to reach (1 - 1/e) = 62% of its final value.  Your
signal starts out at 5V and exponentially decays towards 0.  After 150uS, it
will therefore be at 5V * 1/(e**1) = 1.8V, after two time constants (300uS)
it will be at 5V * 1/(e**2) = 68mV, etc.  The pulse duration depends on
where the input threshold voltage of the second inverter is.  This is
usually specified over a considerable range, so "around 200uS" is probably
as good an estimate as anything since the variation is so high.


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2003\04\20@081005 by Olin Lathrop

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> The time constant RC is based on the voltage rising (or dropping) 67%.

1 - e**-1 = .368, so a one time constant drop reaches 1 - .368 = .632,
making 63% a better value than 67%.

> 67% of 5 volts is 3.35 volts,

It is, but is not relevant here.  The voltage after one time constant = 5V *
e**-1 = 1.84V.

> but if the 2nd invert changes
> state at 4.2 volts, then the pulse width will be longer.

No, it won't.  The exponential decay starts at 5V and goes to 0.  Higher
thresholds will be crossed earlier, making shorter pulses.


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2003\04\20@134027 by James Williams

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> This type of circuit is somewhat of a kludge.  Wanting an edge to
glitch
> converter is usually a symptom of bad design elsewhere.  Note also
that the
> second inverter should be a schmitt trigger unless the RC time
constant is
> very low.

The reason I need a circuit such as this, is because I need an edge
detector.  Also, a prolonged glitch to latch on the S of a latch.  The
edge detector, causes a short pulse on the clock of the flip flop, why
the second glitch circuit has a longer pulse duration and then the state
gets latched into the flip flop.  In my circuit I am interested in
seeing the state of the edge of two signals.  The circuit must determine
if signal A goes from low to high at the same instant as signal B goes
from high to low.  I know that there is another way of doing this, I.E.
latching previous state of two signals, and comparing the previous with
the newly received signals.  But this requires more logic and a fast
processor.  The state of these two signals as a minimun Tw of 0.5us.
The pic processor can not handle this time requirement. Even when
polling.  So I need a circuit that can do the job faster.

Unless there is a better way of doing this.

Regards,


James

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2003\04\20@134031 by James Williams

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Thanks to all who replied.  The biggest thing that I forgot from my
basic electronics is that the capacitor acts as a short initially.  So
then that clears up the question.  I did dig out my first year
electronics book last night.  This type of circuit is defined as a RC
differentiator.  As I can see, this type of circuit has many good uses:
Including a DC charge pump, for generating both a positive and negative
supply rail from a single positive rail.  So I fail to see how this can
be a bad design circuit.

{Original Message removed}

2003\04\20@174929 by Mike Singer

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> Olin wrote:
> > This type of circuit is somewhat of a kludge.  Wanting
> > an edge to glitch converter is usually a symptom of bad
> > design elsewhere.


James Williams wrote:
> The state of these two signals as a minimun Tw of 0.5us.
> The pic processor can not handle this time requirement.
> Even when polling.  So I need a circuit that can do the
> job faster.
> Unless there is a better way of doing this.

How about counting 40MHz signal through time-gates formed
by these two signals? You can quickly store counter's values
to PIC RAM and analyze them late.

  Mike.

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2003\04\20@205915 by James Williams

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> How about counting 40MHz signal through time-gates formed
> by these two signals? You can quickly store counter's values
> to PIC RAM and analyze them late.

>   Mike.

This won't work, because I have .5us to respond to these signals.

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2003\04\20@211533 by Bob Ammerman

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Calling this circuit a kludge comes from a general negative attitude toward
asynchronous circuits such as this. While such circuits are often more
difficult to analyze and debug, sometimes they really are the way to go.

Much early digital circuitry depended heavily on these kinds of 'tricks',
but with more advanced design techniques and cheaper transistors they become
more or less deprecated.

This application looks to me like a good case for using such circuits.

Bob Ammerman
RAm Systems

{Original Message removed}

2003\04\22@054807 by Bill & Pookie

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Add another inverter and you may have an
oscillator?  A word of warning though, you are
playing with devices that use VOLTAGE to operate
rather than CURRENT as the old TTL circuits do.
So this will not work with TTL stuff.

Bill

{Original Message removed}

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