by Bob Ammerman [RAMMERMAN at PRODIGY.NET]
The maximum jitter on a PIC is one cycle. This is because some instructions take one cycle and others take two cycles. It is possible to completely dejitter the PIC by examining the value of the timer register in the interrupt handler. For example, I use the following code on an 18C to do exactly that:
org 8 ; The next two instructions are used to eliminate jitter on the ; interrupt timing. When the interrupt occurs, it may have to wait ; an extra cycle becuase a two cycle instruction is in progress. ; ; We can tell the difference by looking at the least significant ; bit of TMR2. If the next instruction skips we use 2 cycles, if it ; doesn't skip then we use 3 cycles. The net result is that we add ; a cycle when needed so that we always get to 'dejittered' at the ; exact same time relative to the actual rollover of TMR2! btfsc TMR2,0,A bra dejittered dejittered:
Note that this technique should work on all PICs.
Also, on an 18C external interrupts are dejittered by the PIC hardware, as noted by this quote from the last paragraph of section 7.0 of the 18C452 datasheet:
>For external interrupt events, such as the INT pins or >the PORTB input change interrupt, the interrupt latency >will be three to four instruction cycles. The exact >latency is the same for one or two cycle instructions.
I don't believe that external interrupts are dejittered by any prior PIC families. Please correct me if I am wrong.
So, my conclusion is that for timer and external interrupts the 18C can process the interrupt with zero jitter. Non 18C chips can do that for timer interrupts but not external interrupts.
(contract development of high performance, high function, low-level software)
[ed: note that the Scenix SX PIC clones are completely deterministic with reguard to timer and external interrupts ]
|file: /Techref/microchip/isrdejit.htm, 2KB, , updated: 2008/2/26 01:51, local time: 2018/1/23 06:11,
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