Q is the value in the internal register corresponding to the output pin.
Usual CMOS output: When Q is high, P is off and N is on. When Q is low, P is
on and N is off.
(TTL is the same except P is PNP and N is NPN)
Vcc-------+ | ---[ P channel FET | | Q ---| +----------Out | | ---[ N channel FET | Vss-------+Open drain output: When Q is high, N is on, output sinks current. When Q is low, N is off, output is high-impedance.
Vcc-------+ (a pullup resistor between Vcc and Out gives you a logic 1 when N is off) +--------- Out | Q ---[ N channel fet | Vss-------+
file: /Techref/logic/opencollector.htm, 1KB, , updated: 2005/7/27 08:34, local time: 2024/12/2 17:53,
owner: JMN-EFP-786,
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