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IEEE 1284 Electrical Interface

The original parallel port did not have a defined electrical specification that identified the driver, receiver, termination and capacitance requirements in order to guarantee any compatibility between devices. Host adapters and peripherals were built with any number of pull-up values on the control lines, open collector or totem pole drivers for the data and control lines, and most offensive of all, up to 10,000pF capacitors on the data and strobe lines. This type of design variation makes it impossible to create a new interface protocol without explicitly defining the required electrical parameters with which to guarantee operation.

The 1284 standard defines two levels of interface compatibility, Level I and Level II. The Level I interface is defined for products that are not going to operate at the high speed advanced modes, but need to take advantage of the reverse channel capabilities of the standard. The Level II interface is for devices that will operate in the advanced modes, with long cables, and at the higher data rates. This discussion will deal primarily with Level II interfaces. Please refer to the standard for the full requirements for either a Level I or Level II interface.

The requirements for the Level II drivers and receivers are defined at the connector interface. The driver requirements are:

  1. The open circuit high-level output voltage shall not exceed +5.5V.
  2. The open circuit low-level output voltage shall be no less than -0.5V.
  3. The DC steady state, high-level output voltage shall be at least +2.4V at a source current of 14mA.
  4. The DC steady state, low-level output voltage shall not exceed +0.4V at a sink current of 14mA.
  5. The driver output impedance (Ro), measured at the connector, shall be 50 +/- 5 ohms at 1/2 the actual driver Voh minus Vol voltage.
  6. The driver slew rate shall be 0.05-0.40 V/nS

Like the driver requirements, the receiver requirements are defined at the connector interface. The receiver requirements are:

  1. The receiver shall withstand peak input voltage transients between -2.0V and +7.0V without damage or improper operation.
  2. The receiver high-level input threshold shall not exceed 2.0V
  3. The receiver low-level input threshold shall be at least 0.8V.
  4. The receiver shall provide at least 0.2V input hysteresis, but not more than 1.2V.
  5. The receiver high-level sink current shall not exceed 20uA at +2.0V.
  6. The receiver low-level input source current shall not exceed 20uA at +0.8V.
  7. Circuit and stray capacitance shall not exceed 50pF.

Figure 1 shows the recommend termination for a driver/receiver pair. Ro represents the output impedance at the connector. It is intended that this impedance match the cable impedance so as to minimize the noise caused by mismatched impedances. Depending upon the type of driver used, a series resistor, Rs may be required to obtain the correct impedance.

Figure 1 -- Level II Driver/Receiver Pair Termination Example

Figure 2 shows the recommended termination for a Level II transceiver pair, such as the data lines.

Figure 2 -- Level II Transceiver Termination Example

There are products being introduced by companies such as Texas Instruments and National that provide integrated solutions for a 1284 Level II interface. These include active drivers and receivers as well as resister sip networks.

NOTE: When ECP was first introduced Microsoft made a recommendation for an electrical and termination requirement that was not consistent with the 1284 specification. This included an AC terminator for each of the lines. This suggestion has since been retracted and the current recommendation is to use the interface defined in the IEEE 1284 specification.

See also:


file: /Techref/io/parallel/1284/1284elec.htm, 4KB, , updated: 1999/2/28 06:16, local time: 2017/11/20 01:31,
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