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Trinary A2D ?

Russell McMahon suggests

Classically an R2R ladder is used to implement a Successive approximation Analog to Digital converter with drives being high or low. It seems to me that a ternary converter using high/low/open-circuit outputs should allow more resolution per pins used (by a factor of up to 3^N/2^N).

Initial playing on paper produced some ideas (I should be able to get "8 bit" accuracy with 6 pins used) but I may be missing something obvious. Theory says 5 pins SHOULD allow 1 part in 243 but obvious implementation escapes me at this stage.

James Newton tried:

I could see that one problem would be the case when no resistance connected the output to either VCC or GND or when no resistance connected the output to VCC AND GND (all tri-stated) so I assumed the existence of a voltage divider that is always connected to VCC and GND. I label this R3/R4 and assume the ratio of R3 to R4 to be 1 (R3=R4). I then created an MS Excel spread sheet and setup columns for three other resisters (R1, R2, R3) with sub-columns for each containing a zero or a 1 to indicated their possible connection to GND or VCC. Each resistor can be connected to GND, VCC, or nothing. I then entered the formulas necessary to calculate the total resistance of the center point to GND and another for VCC. The ratio of the two is multiplied by the value of VCC to give the voltage at that point. I added a column to show the difference between each successive case and a standard deviation at the bottom of the column.

Results: Although I can't say why, the steps are not perfectly even for any reasonable values of R1-R4.

Russell McMahon replys:

It seems to me that with an output R like this you can pull it up in various binary combinations or not AND down {by the same amounts}so you get N bits above or below ground (or below the centre poinbt in your case) so this is a "win" of 1 extra bit. This is not enough.

The real gain should be 3^m/2^n.

eg for 8 bits base 2 gives 2^8 = 256 states and base 3 gives 3^8 = 6561 states.

Base 2 needs 12.67 bits to achieve this.

Clearly this is not reaaly going to happen as there are several states which are badlky behaved eg all tristate while base 2 has no invalid states.

Mayhaps true base 3 with the third state being mid rail would give a more workable solution This could be APPROXIMATED by a stiffish pullup and pulldown at each pin and a much higher value of R from the pin to the network. eg 1K pullup, 1K puuldown and 100K say to network. Pin hi looks like 100K to high Pin low looks like 100K to low Pin o/c looks like 100.5K to half supply. Using 10k/10k/100k gives 100k/100k/105K in the last example.

Mayhaps the MSBs could use 1K's (about 1 part in 200 MSB resistance error at mid state and LSBs use 10k's - the accuracy of LSB R's in an R/2R can be much lower than the MSBs AFAIR.

See also:


file: /Techref/io/3r2ra2d.htm, 3KB, , updated: 2001/1/16 14:34, local time: 2019/12/7 10:00,
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