[Menu]>[CPLD]


10bits Shift Register



On this page, I will introduce a 10 bits Shift Register.
The shift register is the register where the input data shifts by 1 bit every time the clock pulse inputs.

Pin lock isn't specified.
As the device, it deals with CPLD(XC9536-PC44).

Source code and Explanation

Fitting report


Operating state table
InputOutput
CLKQ9 - Q0
Q0 = DIN
Q1 = Q0
Q2 = Q1
Q3 = Q2
Q4 = Q3
Q5 = Q4
Q6 = Q5
Q7 = Q6
Q8 = Q7
Q9 = Q8