;
; IR Widget 1.00
; 2006-10-19
;
; Keivn Timmerman
; irwidget [@t] compendiumarcana [d0t] com
; www.compendiumarcana.com/irwidget
;



#ifdef __12C508
	include <P12C508.INC>
	#define	CORE12
	#define FIRSTREG 0x07
#endif
#ifdef __12C508A
	include <P12C508A.INC>
	#define	CORE12
	#define FIRSTREG 0x07
#endif
#ifdef __12C509
	include <P12C509.INC>
	#define	CORE12
	#define FIRSTREG 0x07
#endif
#ifdef __12C509A
	include <P12C509A.INC>
	#define	CORE12
	#define FIRSTREG 0x07
#endif
#ifdef __12F508
	include <P12F508.INC>
	#define	CORE12
	#define FIRSTREG 0x07
#endif
#ifdef __12F509
	include <P12F509.INC>
	#define	CORE12
	#define FIRSTREG 0x07
#endif
#ifdef __12F629
	include <P12F629.INC>
	#define	CORE14
	#define FIRSTREG 0x20
	#define PGMSIZE 1024
#endif
#ifdef __12F635
	include <P12F635.INC>
	#define	CORE14
	#define FIRSTREG 0x20
	#define PGMSIZE 1024
#endif
#ifdef __12F675
	include <P12F675.INC>
	#define	CORE14
	#define FIRSTREG 0x20
	#define PGMSIZE 1024
#endif
#ifdef __12F683
	include <P12F683.INC>
	#define	CORE14
	#define FIRSTREG 0x20
	#define PGMSIZE 2048
#endif

													; Configuration bits
#ifdef CORE12
	__config _CP_OFF & _MCLRE_OFF & _WDT_ON & _IntRC_OSC
#endif
#ifdef CORE14
	__config _CPD_OFF & _CP_OFF & _BODEN_ON & _MCLRE_OFF & _PWRTE_ON & _WDT_ON & _INTRC_OSC_CLKOUT
#endif

	errorlevel -220									; Stupid MPLAB complains about IDLOCS
	org		0x2000									; IDLOCS
	;dw		'I','R','W','0'							; IR Widget Rev 0
	errorlevel +220


BANK1		equ 0x80								; Reduce assembler whining

	radix dec										; Default radix of decimal


													; --- I/O
													; 8 Ground
													;
bCompatMode		equ	0								; 7 74HC Hardware Compatiblility Mode
pCompatMode		equ GPIO							;
bSerTx			equ	1								; 6 Serial data to host PC
pSerTx			equ	GPIO							;
bIRDetect		equ	2								; 5 IR Detector module input
pIRDetect		equ	GPIO							;
bOpMode			equ	3								; 4 Operational Mode
pOpMode			equ	GPIO							;
bOscOut			equ	4								; 3 Osc Out (12F6xx)
													;
bIRDemod		equ	5								; 2 IR Demodulator module input
pIRDemod		equ	GPIO							;
													; 1 Power
													;
asio_out_port	set	pSerTx
asio_out_bit	set	bSerTx


	cblock FIRSTREG									; Registers
	last_time
	time_mask
	asio_data
	asio_flags
	asio_bit_time
	four
	temp1
	endc

	org		0x0000									; - Start of program memory

	nop												;
	clrf	GPIO									; All outputs off
	goto	skip_isr								; Jump over the ISR
													;
	org		0x0004									; - ISR
	goto	$										; Let the watchdog handle this
													;
													;
skip_isr											;
													; - Initiailize periferals
													;
#ifdef CORE12										; 
	movwf	OSCCAL									; Setup OSCCAL
													;
	movlw	(1<<bIRDetect) | (1<<bIRDemod) | (1<<bOpMode) | (1<<bCompatMode)	; Setup TRIS
	tris	GPIO									;
													; *GPWU = 1 - Wake-up on change disabled
													; *GPPU = 0 - WPU enabled
													; T0CS = 0 - Internal clock source
													; T0SE = 0 - Inc on rising edge
													; PSA = 0 - Assign prescaller to TMR0
													; PSx - Prescaler = 5 (1:64) 15625 Hz
	movlw	(1<<NOT_GPWU) | 5						;
	option											;
													;
	movlw	4										; 12 bit instruction set lacks ADDLW
	movwf	four									;
#endif	; CORE12									;
													;
#ifdef CORE14										;
													;
	movlw	(1<<CM0) | (1<<CM1) | (1<<CM2)			; Disable comparator
	movwf	CMCON									;
													;
	call	PGMSIZE-1								; Get OSCCAL
													;
	bsf		STATUS,RP0								; Bank 1
													;
	movwf	OSCCAL ^ BANK1							; Setup OSCCAL
													;
#ifdef ANSEL										;
	movlw	(1<<ADCS0) | (1<<ADCS2)					; Make all pins digital I/O
	movwf	ANSEL ^ BANK1							;
#endif												;
													;
	movlw	(1<<bIRDetect) | (1<<bIRDemod) | (1<<bOpMode) | (1<<bCompatMode)	; Setup TRIS
	movwf	TRISIO ^ BANK1							;
													;
	;movlw	(1<<bIRDetect) | (1<<bIRDemod) | (1<<bOpMode) | (1<<bCompatMode)	; Setup WPU
	errorlevel -219									;
	movwf	WPU	^ BANK1								;
	errorlevel +219									;
													;
													; *GPPU = 0 - WPU enabled
													; INTEDG = 0
													; T0CS = 0 - Internal clock source
													; T0SE = 0 - Inc on rising edge
													; PSA = 0 - Assign prescaller to TMR0
													; PSx - Prescaler = 5 (1:64) 15625 Hz
	movlw	5										;
	movwf	OPTION_REG ^ BANK1						;
													;
	bcf		STATUS,RP0								; Bank 0
													;
#endif	; CORE14									;
													;
													; - Initialize registers
													; 
													; Mask for pulse time
	movlw	0										; All 8 bits for micro version
	btfss	GPIO,bCompatMode						;
	movlw	0xC0									; Only 6 bits for 74HC compatible mode, upper two
													;  bits are always 1
	movwf	time_mask								;
													;
	clrf	last_time								; Init last pulse time
													;
													; Setup bit rate
	movlw	0xFF									; 57600 bps (special case)
	btfss	GPIO,bCompatMode						;
	movlw	4000000 / 4 / 19200 - 26				; 19200 bps for compatibility with 74HC hardware
	movwf	asio_bit_time							;
													;
													;
													; Check operational mode
	btfss	pOpMode,bOpMode							;
	goto	irw_count								; Pulse count mode...
													;  ...else pulse time mode...
													;
													;
													; ----- Pulse time capture -----
													;
ptwf												; - Wait for falling edge
	clrwdt											;
	btfsc	pIRDemod,bIRDemod						;
	goto	ptwf									;
													; - Send elapsed time to host
	movf	last_time,W								; Get last time
	subwf	TMR0,W									; Subtract last time from current time
													; W now holds elapsed time
	addwf	last_time,F								; Update last time
	iorwf	time_mask,W								; Mask
	call	asio_tx									; Send to host
													;
ptwr												; - Wait for rising edge
	clrwdt											;
	btfss	pIRDemod,bIRDemod						;
	goto	ptwr									;
													;
#if 0												; * This can be enabled to allow both rising and falling edge
													; *  times to be sent to host. This allow the on/off response
													; *  skew to be observed.
													; - Send elapsed time to host
	movf	last_time,W								; Get last time
	subwf	TMR0,W									; Subtract last time from current time
													; W now holds elapsed time
	addwf	last_time,F								; Update last time
	iorwf	time_mask,W								; Mask
	call	asio_tx									; Send to host
#endif												;
													;
	goto	ptwf									; Loop...
													;
													;
													;
													; ----- Pulse count capture ------
													;
													; - Macros for 4 and 5 cycle delays used for serial
													;    tx timing
													;
													; The 12 bit core lacks a return instruction, so
													;  the 4 and 5 cycle delays will be inline code.
													;  A subroutine call would end with retlw, and that
													;  would corrupt the W register that is used in the
													;  serial tx code.
#ifdef CORE12										;
													;
delay4 macro										; 4 cycle delay
	goto	$+1										;
	goto	$+1										;
	endm											;
delay5 macro										; 5 cycle delay
	goto	$+1										;
	goto	$+1										;
	nop												;
	endm											;
													;
#endif												;
													;
#ifdef CORE14										; The 14 bit core has a return instrucion, so subroutines
													;  can be used for delays
													;
delay4	macro										; 4 cycle delay call
	call	dly4									;
	endm											;
delay5 macro										; 4 cycle delay call
	call	dly5									;
	endm											;
													;
dly5												; 5 cycle delay subroutine
	nop												;
dly4												; 4 cycle delay subroutine
	return											;
													;
#endif												;
													;
irw_count											; - Change the TMR0 clock from internal to external. This
													;    must be done as specified in the data sheet to avoid
													;    false trigger of the watchdog timer.
#ifdef CORE12										;
	clrwdt											;
	clrf	TMR0									;
	movlw	(1<<NOT_GPWU) | (1<<T0CS) | (1<<T0SE) | (1<<PSA) | 7
	option											;
	clrwdt											;
													; *GPWU = 1 - Wake-up on change disabled
													; *GPPU = 0 - WPU enabled
													; T0CS = 1 - External clock source
													; T0SE = 1 - Inc on falling edge
													; PSA = 1 - Assign prescaller to WDT
													; PSx - Prescaler = 0 (1:1)
	movlw	(1<<NOT_GPWU) | (1<<T0CS) | (1<<T0SE) | (1<<PSA)
	option											;
#endif												;
													;
#ifdef CORE14										;
	clrwdt											;
	clrf	TMR0									;
	bsf		STATUS,RP0								; Bank 1
													;
	movlw	(1<<T0CS) | (1<<T0SE) | (1<<PSA) | 7	;
	movwf	OPTION_REG ^ BANK1						;
	clrwdt											;
													; *GPPU = 0 - WPU enabled
													; INTEDG = 0
													; T0CS = 1 - External clock source
													; T0SE = 1 - Inc on falling edge
													; PSA = 1 - Assign prescaller to WDT
													; PSx - Prescaler = 0 (1:1)
	movlw	(1<<T0CS) | (1<<T0SE) | (1<<PSA)		;
	movwf	OPTION_REG ^ BANK1						;
													;
	bcf		STATUS,RP0								; Bank 0
#endif	; CORE14									;
													;
ircw												; - Wait for the host signal to proceed
	clrwdt											;
	btfss	pOpMode,bOpMode							;
	goto	ircw									;
													;
													; --- Count pulses and send to host every 100 microseconds ---
ircl												;
	clrwdt											; 93
	movf	TMR0,W									; 94  Get pulse count
	btfss	GPIO,bCompatMode						; 95  Set upper 2 bits for 74HC hardware compatibility
	iorlw	0xC0									; 96
	movwf	temp1									; 97  Save pulse count
													;
	movf	GPIO,W									; 98  Get port output latch
													;
													;       115200 bps bit times
													;			0.00	8.68	17.36	26.04	34.72
													;			43.40	52.08	60.76	69.44	78.13
													;
	iorlw	(1<<asio_out_bit)						; 99  Start bit - high
	movwf	GPIO									; 0
	delay5											; 1
													;
													;    Bit 0
	andlw	~(1<<asio_out_bit)						; 6  Assume bit 0 is a 1, drive output low - tx data is inverted
	btfss	temp1,0									; 7  Test it
	iorlw	(1<<asio_out_bit)						; 8  It is a 1, not zero, drive output high
	movwf	GPIO									; 9  Update output
	delay4											; 10
													;
	andlw	~(1<<asio_out_bit)						; 14 Bit 1
	btfss	temp1,1									; 15
	iorlw	(1<<asio_out_bit)						; 16
	movwf	GPIO									; 17
	delay5											; 18
													;
	andlw	~(1<<asio_out_bit)						; 23 Bit 2
	btfss	temp1,2									; 24
	iorlw	(1<<asio_out_bit)						; 25
	movwf	GPIO									; 26
	delay5											; 27
													;
	andlw	~(1<<asio_out_bit)						; 32 Bit 3
	btfss	temp1,3									; 33
	iorlw	(1<<asio_out_bit)						; 34
	movwf	GPIO									; 35
	delay4											; 36
													;
	andlw	~(1<<asio_out_bit)						; 40 Bit 4
	btfss	temp1,4									; 41
	iorlw	(1<<asio_out_bit)						; 42
	movwf	GPIO									; 43
	delay5											; 44
													;
	andlw	~(1<<asio_out_bit)						; 49 Bit 5
	btfss	temp1,5									; 50
	iorlw	(1<<asio_out_bit)						; 51
	movwf	GPIO									; 52
	delay5											; 53
													;
	andlw	~(1<<asio_out_bit)						; 58 Bit 6
	btfss	temp1,6									; 59
	iorlw	(1<<asio_out_bit)						; 60
	movwf	GPIO									; 61
	delay4											; 62
													;
	andlw	~(1<<asio_out_bit)						; 66 Bit 7
	btfss	temp1,7									; 67
	iorlw	(1<<asio_out_bit)						; 68
	movwf	GPIO									; 69
	delay5											; 70
	goto	$+1										; 75
													;
	andlw	~(1<<asio_out_bit)						; 77 Stop bit - low
	movwf	GPIO									; 78
													;
	movlw	3										; 79 Sample interval is 100 uS (139 uS for 74HC compatibility)
	btfss	GPIO,bCompatMode						; 80
	movlw	16										; 81
	movwf	temp1									; 82
	decfsz	temp1,F									;
	goto	$-1										;
													;
	goto	ircl									; 91,92
													;
													;
													;
													; ----- Async serial transmission -----
asio_tx												;
	bsf		asio_out_port,asio_out_bit				; Start bit
	clrwdt											; Clear watchdog
	movwf	asio_data								; Move W to tx data register
	movlw	9										; 8 data bits + stop bit
	movwf	asio_flags								;
	call	asio_delay								; Wait one bit time
	nop												;
asiotbl												;
	rrf		asio_data,F								; Shift out a bit
	btfsc	STATUS,C								; Is it a zero?
	goto	$+4										; No..
	nop												; Precise timing
	bsf		asio_out_port,asio_out_bit				;
	goto	$+3										;
	bcf		asio_out_port,asio_out_bit				;
	goto	$+1										;
	call	asio_delay								; Wait one bit time
	decfsz	asio_flags,F							; Dec bit count
	goto	asiotbl									; Not zero, do next bit...
	retlw	0										; Return
													;
													;
													;
asio_delay											; --- Delay N + 14 cycles with one cycle granularity
													;  Special case of 0xFF will delay only 9 cycles
													; W=1, C=1 upon exit
													;
	comf	asio_bit_time,W							; Get compliment of bit time to W
	bsf		STATUS,C								; Carry must be set upon exit
	btfsc	STATUS,Z								; Test for special case of max bit rate (0xFF)
	retlw	1										; Max rate, exit without delay...
	btfsc	asio_bit_time,0							; Add one cycle if bit 0 of bit time is set
	goto	$+1										;
	btfss	asio_bit_time,1							; Add two cycles if bit 1 of bit time is set
	goto	$+3										;
	goto	$+1										;
	nop												;
#ifdef CORE12										;
	addwf	four,W									; 12 bit core lacks addlw, so use addwf with a constant
													;  stored in a register
#else												;
	addlw	4										; Add 4 to W until overflow
#endif												;
	btfss	STATUS,C								;  Each loop interation takes 4 cycles
	goto	$-2										;
	retlw	1										; Set W to 1 and return
													;
													;
													;
	end												;
													;