Digital Signal Processing Logic

From Leslie Yip:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

Entity D_FILTER is
  port( CLK,NRST: in std_logic;
            S_IN: in std_logic_vector(1 downto 0);
            DFIR: in std_logic;
            S_OUT: out std_logic_vector(1 downto 0)
            );
end D_FILTER;

architecture D_FILTER_ARCH of D_FILTER is
signal countA: std_logic_vector(1 downto 0);
signal countB: std_logic_vector(1 downto 0);
signal DS_OUT: std_logic_vector(1 downto 0);

begin

process(CLK, NRST)
begin
if NRST='0' then
     countA <= (others=>'0');

elsif CLK='1' and CLK'event then
     if S_IN(0) ='1' and countA /= 2 then
       countA <= countA + 1;
     elsif S_IN(0) ='0' and countA /= 0 then
       countA <= countA - 1;
     end if;
end if;
end process;


process(CLK)
begin
--if DFIR = '1' then
--  S_OUT <= S_IN;
--else
if CLK='1' and CLK'event then
  if countA=2 then
    DS_OUT(0) <= '1';
  elsif countA = 0 then
    DS_OUT(0) <= '0';
  end if;
end if;
--end if;
end process;

process(DFIR, S_IN, DS_OUT)
begin
if DFIR = '1' then
  S_OUT(0) <= S_IN(0);
else
  S_OUT(0) <= DS_OUT(0);
end if;
end process;


process(CLK, NRST)
begin
if NRST='0' then
     countB <= (others=>'0');

elsif CLK='1' and CLK'event then
     if S_IN(1) ='1' and countB /= 2 then
       countB <= countB + 1;
     elsif S_IN(1) ='0' and countB /= 0 then
       countB <= countB - 1;
     end if;
end if;
end process;


process(CLK)
begin
--if DFIR = '1' then
--  S_OUT <= S_IN;
--else
if CLK='1' and CLK'event then
  if countB=2 then
    DS_OUT(1) <= '1';
  elsif countB = 0 then
    DS_OUT(1) <= '0';
  end if;
end if;
--end if;
end process;

process(DFIR, S_IN, DS_OUT)
begin
if DFIR = '1' then
  S_OUT(1) <= S_IN(1);
else
  S_OUT(1) <= DS_OUT(1);
end if;
end process;

end D_FILTER_ARCH;

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