(this page in work)
We have now reached the level of an entire CPU (Central Processing Unit) which can accept an instruction from memory, execute it, and continue on to the next. How does this work?
1. The opcode is placed in a register, the Instruction Register. The output of that register is decoded. E.g. if one field (set of bits) is the operation type (e.g. load, store, math, etc..), then the microcode interpreter pointer is loaded with a value from a lookup table based on that value. The "lookup" could be as simple as shifting the field value left a few bits. If the longest microcode sequence is 4 steps, the type field might be shifted left 2 places.
2. The microcode engine then takes its current count and produces a set of control signals based on its value. Think of a binary to decimal decoder chip, e.g. 4 wires in, with a binary value, and 16 (2^4) wires out, which go into a diode matrix with different control lines activated depending on which decimal output wire is activated.
3. In your example, one of those wires would enable the decoded destination selection bitfield in the Instruction Register to be set to input from the bus; register A would be the dest in your example, then another control line would enable the memory address at the PC to be driven onto the bus. Of course, before that, a prior step in the microcode would trigger the PC to increment to point at the immediate value. This microcode "program" is stepped along by its own clock and counter, performing several steps per each asm instruction.
4. Once the xfer is complete, the next steps in the microcode program will again increment the PC and then select the Instruction Register as the dest and the memory at PC as the source, and then we are on to the next instruction.
5. Note that each microcode step is actually broken up into a few clock "phases". E.g.
1. select source and dest,
2. clock in the data
So two at a minimum. It can be more complex with instruction preload, tricks to simplify microcode, etc... But thats the basic idea.
Also, some people will say that RISC processors have no microcode. Thats sort of true, but its more accurate to say that the microcode has been reduced to one sequence and hard coded, so to speak. If you stick to the destination, operation, source encoding, the Instruction decode is basically always the same.
And this is as far as this tutorial goes. For an excellent review, with practice problems in the form of a game, which continues all the way to a functional CPU example, see:
A 4 bit instruction set doesn't leave much room. How do you get anything done in 4 bits?
16 op codes: 8 sources, 8 destinations, and after destination, the next opcode sets ALU operation, after operation, each source carries out that operation into the destination
Source / Destination can be
|file: /Techref/logic/CPU.htm, 5KB, , updated: 2022/9/2 10:55, local time: 2022/11/30 21:44,
|©2022 These pages are served without commercial sponsorship. (No popup ads, etc...).Bandwidth abuse increases hosting cost forcing sponsorship or shutdown. This server aggressively defends against automated copying for any reason including offline viewing, duplication, etc... Please respect this requirement and DO NOT RIP THIS SITE. Questions?|
<A HREF="http://techref.massmind.org/Techref/logic/CPU.htm"> CPU, Central Processing Unit</A>
|Did you find what you needed?|
Welcome to massmind.org!
Welcome to techref.massmind.org!