please dont rip this site

massmind : applications : CAD : PWB CAD : Protel : PWB design flow

prev: protel_about.htm -- next: PWB_libraries.htm updated 2006-04-20.

design flow

Here's the basic sequence of steps you go through when you work on a PWB (printed wiring board) using CAD design software. The details are Protel-oriented, since that's what I know, but most PWB CAD tools are similar.

If you have a Protel document that someone has already set up properly, it's easy to make minor changes to the PWB. The typical sequence goes like this:

  1. You get the bad news: "Oops. The holes are too far apart for Component X on Board Y. Move them closer together on the next revision, OK ?".
  2. You find the ".ddb" file for Board Y, double-click on it, then find the ".PCB" file.
  3. You increment the revision number on the silkscreen on the board.
  4. You make some changes to the board.
  5. Hit "Tools | Design Rule Check | Run DRC" to run a design rules check. [Why doesn't typing T D R work ?]. All too often your "fixes" cause other problems. Return to step 4.
  6. Hit the "Explorer" tab on the far left. Find the file of type ".cam", click it, and then hit F9. All the Gerbers, the Drill Drawing, the Drill Guide, the BOM, and other files will be generated and placed in "CAM for..." folder inside the ".ddb" file and copied to a (hopefully appropriate) direction elsewhere on your hard drive.
  7. You exit Protel, find the new Gerbers. You copy a "readme.txt" file into that folder. You right-click on the folder they are in and choose "Add to CAM.zip". Then rename the file to [part number][revision number] ".zip".
  8. Email the ".zip" file to your favorite board house(../pcbfabs.htm), *and* another copy to your favorite assembly house. The assembly house makes stencils from the ".GTP" (if you have SMT components on top) and ".GBP" (if you have SMT components on bottom) files while the board house is etching the board.
  9. Find the parts listed in your BOM, buy them, and send them to your assembly house.

getting started

If you don't have a Protel document that someone has already set up properly, it's up to you.

Generally starting from "scratch" you draw a schematic #start_schematic, simulate it (or manually prototype it on solderless breadboards), then lay it out #start_layout.

Getting started on a schematic

The default ERC matrix is pretty good. Most people change "Project | Project Options... | Connection Matrix" (was: ``Tools | ERC | Rule Matrix'') so that the entire ``Unconnected'' row and column is warnings and errors.

See ``input port'' for an explaination of why the input port row and column is identical to ``output pin''.

``The main change to the ERC matrix that I'd suggest over the default is to set the "Unconnected" row and column to either warning (yellow) [or error (red)] instead of No Report (green). This will require you to put a "No ERC" marker on any unconnected pins, but that seems like a good idea, anyway.

The other change I made was to make the "Unspecified Port" row and column all error (red), as I don't want to have ANY port unspecified. '' -- Dwight Harm Trax Softworks, Inc. 2001-06-12

Getting started on a layout

If you already have a board designed using some other software, it's often quicker and more accurate to try to import those design files into Protel than to start from scratch. Check out the conversion tools .

When you're doing a new board "from scratch", the easiest way to start a new layout (assuming you already have a schematic):

In theory, the correct footprints for all your components should show up in a big pile to the right of the board. But I've never seen that happen perfectly the first time. While looking at the PWB, you'll need to "add" libraries of footprints. When you find the right shape in the footprint library, remember the name of that footprint, then flip back to the schematic. While looking at the schematic, you'll need to double-click the components and make sure the right footprint name is filled in each "footprint" box. Typically you change a few things and do step (4), change a few more things, repeat until all the footprints look right.

Then you'll want to set up "Design rules" for minimum hole size, minimum annular ring, etc. (... vias ...)

Draw 50 mil tracks on the keep-out layer, "continuous" (the start of one track snapping exactly to the end of the last track), centered on the board edge, completely around the board. (This forces tracks on the signal layers to stay at least 25 mil away from the board edge). Set up a design rule to force components to stay even further away from the edge.

Draw 60 mil tracks on the ground plane centered on the board edge, completely around the board. Do the same for every power plane. This makes the copper plane stop 30 mil way from the board edge. (If the planes run all the way to the edge, then they will be exposed after routing, and it would be very easy for them to short together). [FIXME: would it be better to run *only* the ground plane right up to the edge ?]

Here's some settings/preferences that seem to cause a lot of unnecessary trouble.

Q: Can Protel handle large boards ?

Protel can handle some huge boards. Size Of board 23.359 x 15.88 sq in 2600 components, 19,823 pads, 13,464 vias http://www.dunneroberts.co.uk/progallery/big-body.htm [FIXME: has this gone offline ?]

The mouse-wheel problem ... [FIXME]

schematic

large schematic designs

When you do a large design, it's worth your time to learn about global operations. ``global operations ... the single greatest feature of Protel ... very powerful and well worth spending a day to understand.'' -- Ian Wilson. You'll find them very useful in both the schematic editor and the PWB layout editor.

With large schematic designs, it helps reduce clutter to use busses and hierarchy. If you have several sections that are almost identical (say, independent filters and amplifiers for Left and Right stereo channels), it's helpful to put the duplicated stuff on one sheet (``one channel''), and include 2 copies of the sheet symbol on the top-level schematic page. Then any changes you make on that page of the schematic are automatically made to both channels of the PWB.

[For the purpose of making connections between sheets,] ``Bus labels/names are in the format P[0..15], which includes the nets P0 through to P15 (please note the square brackets and the two dots). No other naming convention is accepted. . You cannot group/bus nets with names such as "clk", "data", "strobe", etc. You cannot assign a bus a name such as "i2c".'' -- Brendon Slade on 2001-01-03 [It's fine to name a bus "i2c" on a single sheet, and attach wires net-labeled "clk", "data", etc. to it.]

``I've used (and liked!) the hierarchical sheet support, with "Sheet Symbol/Port Connections" selected for netlists, synch, and ERC. ... [If] I set "Net labels and ports global", my sheet entries that were connected on a top-level schematic page no longer appear connected, unless the port names are identical. Essentially, any wiring between sheets at the top-level is now meaningless -- it has no effect on the netlist.'' -- Dwight Harm 2001-01-02

``global is evil, as I often want to use a sheet several times in a design...'' -- Dwight Harm 2001-01-02

Dwight Harm 2001-01-03 :

  1. Port names do not need to match bus net names, but should have the identical numeric range, e.g., "[0..7]".
  2. Port names must match sheet entry names exactly (just as they do for single signals).
  3. On the upper level schematic, the sheet entries must be connected by a bus. The bus may be named or unnamed. The only restriction on the name is that it have the same numeric range. The textual part is irrelevant.

symbols for schematic

(schematic library design tips for making new symbols.)

If you want a symbol that's not already in the schematic symbol libraries , then you must make it yourself in your own library.

See PWB_libraries.htm#symbols

Layout

In an ideal world, layout would consist of

  1. (1) setting up: drawing the outline of the board, marking and locking mechanical areas.
  2. (2) placing the components with auto-place,
  3. (3) connecting the components with auto-route.

In reality (as of 1999), one usually does 

(1) setting up: drawing the outline of the board, marking and locking mechanical areas.
(1b) "Design Options Options" and pick reasonable grid values
  (25 mil grid was popular with all-through-hole boards;
  10 mil grid (exactly 0.254 mm) seems to be popular with surface-mount boards)
(2)  place components with auto-place
(3)  laugh at the stupidity of today's computers
(4)  Manually group components by going to the schematic,
	selecting a related group of components, doing "Tools | Select PCB components",
	and moving each group near the final position, using human intuition to place each group.
(5)  Use human intuition to shuffle the components of each group.
	If each group can be packed into a small rectangle (a "room"),
	and there is enough room on the board
	to place every rectangle ("room") without overlapping,
	then that makes things easier.
(6)  route "critical nets" and lock them down
(7)  auto-route
iterate:
  (8) move component(s) to make more room in congested areas
  (9) Put in traces you just made more room for
  (10) re-connect component(s) you just moved
  (11) Do DRC
until everything's wonderful.

The next step after Layout is creating the CAM files to go to manufacturing.

board outline

setting up: drawing the outline of the board, marking and locking mechanical areas.

Draw (typically on layer Mech 2) the outline of the board, where all the mounting screws go, and where mechanical constraints are. Leave that layer on while placing components so you know what to work around.

(slots, "rectangular holes", concave boards, ...)

"Hamid A. Wasti" on 2001-02-12 wrote:

Subject: Re: [PROTEL EDA USERS]: Rectangle holes

Brad Velander wrote: 

> a typical shop might have a 32mil diameter
> router as their smallest size
> router bit and therefore your corners will have a 16mil radius.

It is a bad idea to use an inside radius same as your router bit radius. This requires the router to come to a complete stop and then start moving at 90 degrees. There will invariably be some chatter and the router will cut into the sides. It is better to make a minimum radius larger than the router radius so the cut is programmed as an arc which will give a lot better results.

Hamid

Many people put layer stack-up text (also called a ``layer name block'') in some unused corner of the PWB: (see ../pwb_layers.htm )

I always create a "layer stack-up window" on each copper layer of the PCB. (i.e. The top will have a "1", the next layer a "2" etc.) For a 6 layer board you will see a strip of numbers 123456. Leave the solder mask off the top & bottom around this strip. That way you can hold the "window" up to the light & confirm that they actually built the stack-up you requested, and you don't need to cut up a test coupon. You have to remember to "draw" the numbers as negatives for the plane layers, because you are actually drawing non-copper. Remember to leave copper off all layers around this window, so the board is somewhat transparent.

-- Mark Geddes

Dennis Saputelli put his version online: http://www.egroups.com/files/protel-users/stack2.zip

Ian Wilson further explains:

So in words: If I have layer 3 as a negative plane layer, I will simply have a numeral "3" on the layer. To the left I will have a small fill, just large enough to remove copper under the numerals "1" and "2" and to the right I will have another fill, just large enough to remove the copper under "4", "5" and "6" (for example). ... Obviously this changes depending upon number of layers and plane distribution. An automatic, Protel-generated, graphic would be useful. ... So each signal layer has just a simple numeral. Each plane layer has the numeral and two fills, one on each side, that allows light to shine through to the board. Sample showing this is available from egroups file store: http://www.egroups.com/files/protel-users/LayerStackSample.zip

Abd ul-Rahman Lomax continues:

I put down, on, say, the fabrication layer, a series of numbers from 1 up to the number of layers. I draw a box around this, using a small track size. This box is on a fabrication layer. I edit each number so that it is on the appropriate layer. On negative layers, I place 50 mil track to fill in all but an area over the number of that layer. ... Since I typically use a 50 mil track to keep negative layers clear from the board edge, that size is available ... The blowouts that are visible through the board, with the plane layer numbers between them, leave an hour-glass type of shape instead of a rectangular box, but this is harmless.

Placement (of components)

Once you've sketched the outline of the board, it's time to place components.

Some people use ``Rooms'' to help put related components in the same general area (digital stuff here, analog stuff there). If you break your schematic into several pages, this automatically happens. If you just have one big schematic, `` Select the components one desires to associate with a room. Design/Classes/Component/Add/Class_Generator/Selection/True and create a class of the selected components. Then assign that class to the room. '' -- Abdulrahman Lomax (2001-04-09)

"virtual short" ("star ground")

One under-appreciated ``component'' is the ``virtual short'', also known as a ``star point'' which can be used as a ``star ground''.

See PWB_libraries.htm#short

Common problems during component placement:

repetition

Q: "I'm designing a board with four amplifier channels. I have a layout that I like and would like the same layout for each channel. What is the best method for doing this ?" -- Roy Frazier

A1:

Select the block and copy it 3 times, then select each one, and use a global edit to replace all part designators with some systematic change, such as replace C101 with C201... C401 like this {C1=C2} and {R1=R2} and {U1=U2} etc. I haven't found a really cute way to do this, although originally naming all parts something like CZ01,CZ02...CZnn, and RZ01,RZ02...RZnn, etc. would make the replace much easier, as {Z=1}, {Z=2}...{Z=4}.

Duplicate the schematic section 3 times [can't you just put one section on a schematic sheet, then refer to that sheet 4 times on the main schematic sheet ?], rename the nets and components with global edits, update the board from the schematic.

Then 

"Design | Netlist Manager | Menu | Update Free Primitives From Component Pads"

to fix the trace nets.

Now, the board should check against the schematic nets without errors.

-- Jon Elson 2000-12-15

A2:

You will probably find the QualEcad http://qualecad.com/ add-in tool useful also. It will automatically generate new designators for selected sections of layout that you have copied. Find it at: http://www.qualecad.com/Reference%20Designator%20Modifier.zip

-- Tim Hutcheson 2000-12-15

Footprint Library design tips

If the footprint you want isn't already in the libraries , then you'll have to make your own footprint.

See Footprint Library design tips for details.

routing

auto-routing

Watch out if you use any copper *tracks* embedded in components. If you run the autorouter on a board with a Protel Sot-89 footprint (or other footprints with embedded tracks) , often the autorouter deletes the "trace" part of the footprint. You then need to refresh the footprint. [Has this bug been fixed ?]

Work-around 1: To stop the auto-router using the space freed by deleting your track you can protect the area with layer-specific keepout tracks and fills. -- Ian Wilson

Work-around 2: make sure those track segments are part of a trace that is terminated at both ends by a pad or via.

...

Under "Design | Rules... | Routing | Routing Layers" there should be one rule. Select it and hit "Properties...". I set the top signal layer to "horizontal", the bottom signal layer to "vertical", before running the autorouter. On some boards setting the top to "vertical", and the bottom to "horizontal", then the autorouter worked better. One might think that giving this autorouter the freedom to choose "Any" would help. When I tried this, it always made a tangled mess.

I've never seen the autorouter complete a board the first time. Usually it's because I put a few components so close together and given the router such difficult constraints, that there is no room to get all those nets routed without some constraint violation.

When the software realizes that it's impossible to complete with the constraints you gave it, it "finishes" with lots of unrouted nets, and sometimes traces that clearly violate your given constraints. If it's really ugly, hit undo (ALT+BackSpace). If it's not too bad, you can leave the traces it put down, and that gives it a starting point to start next time -- faster than starting from scratch.

Find where the routing congestion is, and manually scoot the components in that area further apart (so there's more room for wires between them). Then start the autorouter again.

It can help guide the autorouter to manually route some traces and lock them down. Sometimes manually routing a trace, then running "Tools | Design Rule Check... | Run DRC" helps you find overly-conservative design rule constraints that make it impossible to route a board.

It's really helpful if there are *no* DRC errors before starting the autorouter.

The Multilayer should contain *only* and *all* through-hole pads and vias. Anything else (tracks, text, etc) on the multilayer confuses the autorouter.

------------------- Begin Copied Message -------------------

I have been using P98/SP3 since it first came out. I had some problems similar to yours when I first started using it, then I developed a check list of what to do (and not do) and have had no problems. Several of these are in Protel's Knowledge Base (Item 1694); however, these are what I have found to be effective.

I do Item 1 and 2 since I "never" have a board where the keep out is defined by the actual board edge. If I need a rounded keep out region, I use several short line segments. Several people have commented that they save all mechanical layer information to a separate file and restore it after routing. I don't unless I have routing problems.

Item 7 is extremely important, if I am trying to test route a section, I delete the components not being routed rather than try moving them outside the keep out region. Also beware the object that got moved outside the visible region due to not deselecting it prior to selecting and moving another object!

Item 8 came about when I had a special polygon on the top outline layer even though it was not to affect routing or vias. Removing it allowed the route to proceed normally.

Regarding Item 11, the autorouter will use the maximum width specified for traces, which can be a problem if that trace connects to fine pitch components.

NOTE: using the circuit board wizard violates these guidelines if you plan on autorouting.

------------------- End Copied Message -------------------

Several of the above items should no longer be required (according to the NEW release information); however, it is a good starting point such that any deviations should be well understood...

-- David W. Gulley on 2001-03-28

``To make a circular board you would create the keepout circle(arc) and then surround it with a rectangle so it will work. The router will stay within the circle, but requires the rectangle to initialize.'' -- Colby Siemer http://www.PowerStream.com/

Q: I've done all the above, and my board *still* refuses to auto-route !

A1:

For systematic troubleshooting, there is a generic process I call chunking. Take the design and divide it into two parts, each approximately half of the design. You can do this on the PCB, since nets are carried by the pads. Delete the parts in one half (obviously you are doing this with a copy of your design so you can completely screw it up without losing anything). If the autorouter now runs, the problem is probably in the half you deleted. By extending and following this process recursively, you may be able to find, in a few operations, exactly what part or primitive is causing difficulties.

Obviously, if you change something and it now routes, what you changed almost certainly contains the problem.

Abd ul-Rahman Lomax on 2001-03-28 03:56:11 PM

A2: We're still tracking down some obscure bugs. If you can reduce the board down to a couple of parts that refuse to auto-route, please let us look at it. email one copy to Protel's tech support, and send another copy to a volunteer on the PEDA mailing list. (To get the absolute fastest response, post it on a web page, then email that page's URI to the entire PEDA mailing list).

manual routing

manual routing

Sometimes the autorouter gives a ``net routed 99.8%'' message, leaving just a few traces for you to manually route. Normally doing a DRC helps you jump right to the problem [FIXME: step-by-step explaination ?], except when the net goes all over the board like GND or +3V and there's a unconnected island somewhere.

Q: How do I find the unconnected island ? A: ``My usual approach is to turn off all layers except the Connection layer, leaving just one of the Mech layers turned on to keep from forcing TopLayer on. Zoom out to see the whole board, and you should be able to see the connection, though it's probably very short, just trying to connect pads on opposite sides of the board or similar. Place the cursor on the spot, zoom in to an appropriate level, and then turn the copper layers back on to see what's what. This technique has always enabled me to find the missing connection. It's usually one which I thought was connected! '' -- Steve Hendrix
``Also it may help to turn off any displayed grid.'' -- Abd ul-Rahman Lomax

Q. I just placed some vias and free pads. Why won't Protel let me route traces to them ?

A. Protel normally won't allow you to make the mistake of shorting 2 different nets together. Vias and free pads default to a net property of "No Net".

When I'm placing a track: 

  P T click, click, click, click

Each click of the mouse drops a new segment of track. I try to start routing from something that already has a net. Then I *can* route to a "No Net" via or track by getting close and momentarily turning off "Avoid Obstacle": 

  click, click, shift+R shift+R click, click, shift+R click, click, click ... click Esc Esc.

(It takes at least 2 clicks to place a segment "into" and then "out of" the "No Net" via). Note that I do *not* have to escape out of place-track mode to switch to "Ignore Obstacle" and re-start.

While placing track, the shift+R cycles through "Avoid Obstacle" (my favorite default), "Push Obstacle", and "Ignore Obstacle" modes. The current mode is displayed in the status bar. You might find "Push Obstacle" helpful in tightening up busses.

Later I do a "Design | Netlist Manager | Menu | Update Free Primitives From Component Pads" which changes the net of those "No Net" pads and traces to the net to which I just connected them, to make DRC happy. That update seems very slow on large boards -- be patient. -- David Cary

Q: How do I do "Auto Hugging" ? Auto Hugging is ... ... ???

A: Did you know that you can auto-push other traces out of the way while laying out a trace ? Start placing a track: 

  P T click, click

then hit shift-R until the status bar says "Push Obstacle". Then keep laying track close to, even on top of, traces from other nets. Cool, Eh ?

Remember to hit shift-R to get back to "Avoid Obstacle" when you're done. Also, be sure to run a DRC check before releasing this board, because "Push Obstacle" occasionally doesn't push the other tracks far enough away. (bug/enhancement request: handle placing vias better).

Q: How do I change the color of the Connections layer ? "Tools | Preferences... | Colors", click on the color patch next to "Connections", doesn't seem to do anything.

A: I hope Protel fixes this in the next rev. Meanwhile, While looking at the PCB, under the "Browse PCB" tab at the left side, select "Nets | Edit... | Global", change the color, "OK". (BTW, it's fun to click on the net names in that list). [FIXME: was at http://www.protel.com/kb/kb_item.asp?ID=1175 was http://www.protel.com/kb/rdc1175.htm . Did that dissapear ? Is http://www.protel.com/resources/kb/kb_item.asp?ID=2446 relevant ? ]

"Unfortunately the setting is not maintained as application preference after FILE--->Exit." -- Richard Pikacz on 2000-08-24.

Working with polygons

Some people like to place polygons first, before placing any components, then use the "plow through" setting. Others like to hold off until the board is mostly routed, so it's obvious where polygons should go.

Q: How do I punch a hole (no copper) in the middle of a polygon (solid copper) ?

A1: Draw tracks on the keep-out layer (punches holes in every layer) or draw tracks with the keep-out property on same layer as the polygon.

A2: ``What I do is use a 0.1 mil track to draw features that keep the polygon pour out of select areas. They have a no-net attribute, and conform to existing design rule clearances. During fab, they probably get over-etched into oblivion, but even if they don't, the design rules should have kept them from causing any problems. These tracks can then be left to be persistent, and no worries of having to delete, move, or re-create features every time you need to re-pour or DRC check.'' -- Bruce Walter

Then re-flow the polygons (double-click the polygon, OK, Yes).

(This is different for a #power_plane ) 

From: Duane Foster 
Date: 2000-08-01

> Once I tried checking 'remove dead copper' and
> the area where
> the pour should be briefly flashed but no filled polygon remained.

Danger Danger Danger
That polygon which disappeared is still there.  When you pour another
polygon on top of it, Protel really bogs down.  There is a tech note on
finding hidden polygons and removing them.  The best course is to delete it
when you realize when you have created a hidden polygon (since you just
placed it, you should be able to find it, select and delete it, even though
you cannot see it) (You can also revert to a saved copy if you have saved
before pouring)

This little nuance wrecked my first day with Protel98, new users always
gravitate towards those trouble spots!

Duane Foster

Placing Polygons: Many early PWB designs used the "cherry pie lattice" (hatched) for large copper polygons, using something like a 12 mil track, 24 mil grid. This is because early solder mask didn't stick well to metal, so the array of little square holes in the metal let the solder mask stick to the board better.

Current design practice uses completely solid areas of metal -- for example, 12 mil track, 0 mil grid [*], and 12 mil minimum primitive. [*] "Grid zero causes Protel to pour the grid with tracks exactly next to each other." -- Abdulrahman Lomax

More on the "cherry pie lattice":

Sometimes polygons are just in the way. There are several ways to temporarily get them out of the way:

You usually don't want to Cut and Paste polygons -- the net of the cut polygon is forgotten, and the pasted polygon is "No Net".

"You can never know too many ways of doing something." -- Pat Nystrom

Q: Is there a way to re-pour ALL polygon planes without double-clicking on each one, forcing a re-pour ?

A1: Jason Morgan [mailto:jason.morgan at citel.com] Tuesday, June 05, 2001 2:17 AM created a Server to re-pour all polygons. Ian Wilson put Jason's server online for free download at http://groups.yahoo.com/group/protel-users/files/? .

A2: select | all, move everything 1000 mil up, then select | all, move everything 1000 mil back down. Say ``yes'' to repour polygons.

Working with power planes

Q: How do I punch a hole (no copper) in the middle of a plane (solid copper) ?

A1: Protel automatically does the Right Thing for vias and through-holes that don't connect to that plane.

A2: flip to the appropriate power plane layer (use the tabs near the bottom of the screen), then place track, fills, even polygons in the exact shape of the desired hole. (This is different for #polygons )

Connections to power planes:

Never put "thermal relief" on a via. Always make vias "direct connect" to any polygons or power planes of the same net.[*]

Q: How do I do this ? -- Tom Reineking

Protel does this properly by default for polygons when "Pour over same net" is enabled for that polygon. (The "Design | Rules | Manufacturing | polygon connect style" only applies to "pads".)

Protel does not (yet) do this properly by default for power planes. You must set up rules under "Design | Rules | Manufacturing | power plane connect style" for proper power plane connections. I have 2 rules set up here:

  1. All vias: PlaneConnect_1: connect: Direct, scope: Via Specification: (the Via Selection box has five via selection criteria, each with a check box. Make sure all boxes are empty. An unchecked box is a "don't care" selection criterion.).
  2. All pads: PlaneConnect_2, connect: Relief, scope: Board. ... entries: 4.

-- Michael Beavis and Abd ul-Rahman Lomax

Don't forget some of the clearance rules, and the polygon rules, will restrict the amount of copper poured. This could result in a pad or via that doesn't connect to the pour.

[*] If you *don't* want it to connect, then make it a different net in the schematic, perhaps using the "virtual short" component.

If you *do* want a thermal relief, make it a "pad", not a "via". Select the vias and do Tools|Convert|Convert selected vias to free pads. -- Andy Gulliver

Then update the design rule for relief polygon connection to those pads. [bug: There appears to be a design rule for relief polygon connections for vias. But it doesn't do anything -- they are always direct-connect].

The spokes of "thermal relief" are only used for holes where through-hole components mount. ``Why anyone would want to thermally relieve a via is beyond me.'' -- Abd ul-Rahman Lomax

[bug: there *should* be an "Object Kind" entry in the drop down list of the "Filter Kind" combo box -- Geoff Harland]

[bug: Protel *should* do this properly by default for power planes, just like it already does for polygon planes. ]

[bug: if you pour a polygon over a via, with "pour over same net" turned off, the via will not connect to the polygon. The DRC (Un-Routed Net Constraints) will not detect this unconnected via, even if I route a (GND) track to it! Workaround / Moral: *always* turn on "pour over same net".]

end http://massmind.org/techref/app/pwb_design_flow.htm

See also:

Code:

file: /Techref/app/pwb_design_flow.htm, 57KB, , updated: 2021/6/14 19:44, local time: 2024/12/25 07:36, owner: DAV-MP-E62a,
TOP NEW HELP FIND: 
18.217.228.195:LOG IN
 ©2024 These pages are served without commercial sponsorship. (No popup ads, etc...).Bandwidth abuse increases hosting cost forcing sponsorship or shutdown. This server aggressively defends against automated copying for any reason including offline viewing, duplication, etc... Please respect this requirement and DO NOT RIP THIS SITE. Questions?
Please DO link to this page! Digg it! / MAKE!

<A HREF="http://techref.massmind.org/Techref/app/pwb_design_flow.htm"> next step</A>
After you find an appropriate page, you are invited to your to this massmind site! (posts will be visible only to you before review) Just type a nice message (short messages are blocked as spam) in the box and press the Post button. (HTML welcomed, but not the <A tag: Instead, use the link box to link to another page. A tutorial is available Members can login to post directly, become page editors, and be credited for their posts.


Link? Put it here: 
if you want a response, please enter your email address: 
Attn spammers: All posts are reviewed before being made visible to anyone other than the poster.
Did you find what you needed?
 

Welcome to massmind.org!

 

Welcome to techref.massmind.org!

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

  .